MSP430F643 Datasheet, PDF(15/106 Page) Texas Instruments

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MSP430F643 Datasheet, PDF (15/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

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MSP430F643x

www.ti.com

SLAS720B â AUGUST 2010 â REVISED AUGUST 2012

Interrupt Vector Addresses

The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The

vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 6. Interrupt Sources, Flags, and Vectors of MSP430F643x Configurations

INTERRUPT SOURCE

INTERRUPT FLAG

System Reset

Power-Up, External Reset

Watchdog Timeout, Key Violation

Flash Memory Key Violation

System NMI

PMM

Vacant Memory Access

JTAG Mailbox

User NMI

NMI

Oscillator Fault

Flash Memory Access Violation

Comp_B

Timer TB0

Watchdog Interval Timer Mode

USCI_A0 Receive or Transmit

USCI_B0 Receive or Transmit

ADC12_A

Timer TA0

LDO-PWR

DMA

Timer TA1

I/O Port P1

USCI_A1 Receive or Transmit

USCI_B1 Receive or Transmit

I/O Port P2

LCD_B

RTC_B

DAC12_A (4)

Timer TA2

I/O Port P3

I/O Port P4

WDTIFG, KEYV (SYSRSTIV)(1)(2)

SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,

VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,

JMBOUTIFG (SYSSNIV)(1)

NMIIFG, OFIFG, ACCVIFG, BUSIFG

(SYSUNIV) (1) (2)

Comparator B interrupt flags (CBIV)(1)(3)

TB0CCR0 CCIFG0(3)

TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,

TB0IFG (TBIV)(1) (3)

WDTIFG

UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(3)

UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(3)

ADC12IFG0 to ADC12IFG15 (ADC12IV)(1)(3)

TA0CCR0 CCIFG0(3)

TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,

TA0IFG (TA0IV)(1)(3)

LDOOFFIG, LDOONIFG, LDOOVLIFG

DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,

DMA4IFG, DMA5IFG (DMAIV)(1)(3)

TA1CCR0 CCIFG0(3)

TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,

TA1IFG (TA1IV)(1)(3)

P1IFG.0 to P1IFG.7 (P1IV)(1) (3)

UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(3)

UCB1RXIFG, UCB1TXIFG (UCB1IV)(1)(3)

P2IFG.0 to P2IFG.7 (P2IV)(1) (3)

LCD_B Interrupt Flags (LCDBIV)(1)

RTCRDYIFG, RTCTEVIFG, RTCAIFG,

RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1)(3)

DAC12_0IFG, DAC12_1IFG(1)(3)

TA2CCR0 CCIFG0(3)

TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,

TA2IFG (TA2IV)(1)(3)

P3IFG.0 to P3IFG.7 (P3IV)(1)(3)

P4IFG.0 to P4IFG.7 (P4IV)(1)(3)

SYSTEM

INTERRUPT

Reset

(Non)maskable

Maskable

WORD

ADDRESS

0FFFEh

0FFFCh

0FFFAh

0FFF8h

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

0FFEAh

0FFE8h

0FFE6h

0FFE4h

0FFE2h

0FFE0h

0FFDEh

0FFDCh

0FFDAh

0FFD8h

0FFD6h

0FFD4h

0FFD2h

0FFD0h

0FFCEh

0FFCCh

0FFCAh

PRIORITY

63, highest

(1) Multiple source flags

(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.

(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(3) Interrupt flags are located in the module.

(4) Only on devices with peripheral module DAC12_A, otherwise reserved.

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