MSP430F643 Datasheet, PDF (19/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F643x
www.ti.com
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
Table 11. Port Mapping, Mnemonics and Functions (continued)
VALUE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20-30
31 (0FFh)⁽¹⁾
PxMAPy MNEMONIC
PM_CBOUT
PM_TB0CLK
PM_ADC12CLK
PM_DMAE0
PM_SVMOUT
PM_TB0OUTH
PM_TB0CCR0B
PM_TB0CCR1B
PM_TB0CCR2B
PM_TB0CCR3B
PM_TB0CCR4B
PM_TB0CCR5B
PM_TB0CCR6B
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_MCLK
Reserved
Reserved
Reserved
PM_ANALOG
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
-
Comparator_B output
Timer TB0 clock input
-
-
ADC12CLK
DMAE0 Input
-
-
SVM output
Timer TB0 high impedance input
TB0OUTH
-
Timer TB0 CCR0 capture input CCI0B
Timer TB0: TB0.0 compare output Out0
Timer TB0 CCR1 capture input CCI1B
Timer TB0: TB0.1 compare output Out1
Timer TB0 CCR2 capture input CCI2B
Timer TB0: TB0.2 compare output Out2
Timer TB0 CCR3 capture input CCI3B
Timer TB0: TB0.3 compare output Out3
Timer TB0 CCR4 capture input CCI4B
Timer TB0: TB0.4 compare output Out4
Timer TB0 CCR5 capture input CCI5B
Timer TB0: TB0.5 compare output Out5
Timer TB0 CCR6 capture input CCI6B
Timer TB0: TB0.6 compare output Out6
USCI_A0 UART RXD (Direction controlled by USCI - input)
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI - output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
-
MCLK
Reserved for test purposes. Do not use this setting.
Reserved for test purposes. Do not use this setting.
None
DVSS
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents
when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored,
which results in a read out value of 31.
PIN
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5
Table 12. Default Mapping
PxMAPy
MNEMONIC
PM_UCB0STE,
PM_UCA0CLK
PM_UCB0SIMO,
PM_UCB0SDA
PM_UCB0SOMI,
PM_UCB0SCL
PM_UCB0CLK,
PM_UCA0STE
PM_UCA0TXD,
PM_UCA0SIMO
PM_UCA0RXD,
PM_UCA0SOMI
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
USCI_B0 SPI slave transmit enable (direction controlled by USCI - input),
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)
USCI_A0 UART TXD (direction controlled by USCI - output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 UART RXD (direction controlled by USCI - input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
Copyright © 2010–2012, Texas Instruments Incorporated
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