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MSP430F643 Datasheet, PDF (69/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F643x
www.ti.com
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
12-Bit DAC, Linearity Specifications (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 17)
PARAMETER
EO
Offset voltage
TEST CONDITIONS
Without calibration(1) (3)
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
With calibration(1) (3)
VeREF+ = 1.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
VCC
2.2 V
MIN TYP MAX UNIT
±21 (2)
3V
2.2 V
±21
mV
±1.5 (2)
3V
±1.5
dE(O)/dT
Offset error
temperature
coefficient (1)
With calibration
2.2 V, 3 V
±10
µV/°C
EG
Gain error
VeREF+ = 1.5 V
VeREF+ = 2.5 V
2.2 V
3V
±2.5
%FSR
±2.5
dE(G)/dT
Gain temperature
coefficient (1)
2.2 V, 3 V
ppm
10
of
FSR/
°C
tOffset_Cal
Time for offset
calibration (4)
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
165
66 ms
16.5
(3) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
(4) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect
accuracy and is not recommended.
DAC Output
RLoad = ¥
AVCC
2
CLoad = 100 pF
DAC VOUT
VR+
Ideal transfer
function
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 17. Linearity Test Load Conditions and Gain/Offset Definition
Copyright © 2010–2012, Texas Instruments Incorporated
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