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MSP430F643 Datasheet, PDF (37/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER
MSP430F643x
www.ti.com
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
Table 46. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
USCI control 0
USCI control 1
USCI baud rate 0
USCI baud rate 1
USCI modulation control
USCI status
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
REGISTER
UCA1CTL0
UCA1CTL1
UCA1BR0
UCA1BR1
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
UCA1IFG
UCA1IV
OFFSET
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
Table 47. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
REGISTER
UCB1CTL0
UCB1CTL1
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
UCB1IFG
UCB1IV
OFFSET
00h
01h
06h
07h
0Ah
0Ch
0Eh
10h
12h
1Ch
1Dh
1Eh
Table 48. ADC12_A Registers (Base Address: 0700h)
REGISTER DESCRIPTION
Control register 0
Control register 1
Control register 2
Interrupt-flag register
Interrupt-enable register
Interrupt-vector-word register
ADC memory-control register 0
ADC memory-control register 1
ADC memory-control register 2
ADC memory-control register 3
ADC memory-control register 4
ADC memory-control register 5
ADC memory-control register 6
ADC memory-control register 7
ADC memory-control register 8
REGISTER
ADC12CTL0
ADC12CTL1
ADC12CTL2
ADC12IFG
ADC12IE
ADC12IV
ADC12MCTL0
ADC12MCTL1
ADC12MCTL2
ADC12MCTL3
ADC12MCTL4
ADC12MCTL5
ADC12MCTL6
ADC12MCTL7
ADC12MCTL8
OFFSET
00h
02h
04h
0Ah
0Ch
0Eh
10h
11h
12h
13h
14h
15h
16h
17h
18h
Copyright © 2010–2012, Texas Instruments Incorporated
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