MSP430F643 Datasheet, PDF (57/106 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F643x
www.ti.com
SLAS720B – AUGUST 2010 – REVISED AUGUST 2012
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
(see Figure 11 and )
f_USCI
PARAMETER
USCI input clock frequency
TEST CONDITIONS
SMCLK, ACLK,
Duty cycle = 50% ± 10%
V_CC
MIN TYP
t_SU,MI
SOMI input data setup time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
55
3V
38
2.4 V
30
3V
25
t_HD,MI
SOMI input data hold time
PMMCOREV = 0
PMMCOREV = 3
1.8 V
0
3V
0
2.4 V
0
3V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF,
PMMCOREV = 0
UCLK edge to SIMO valid,
C_L = 20 pF, PMMCOREV = 3
1.8 V
3V
2.4 V
3V
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF, PMMCOREV = 0
C_L = 20 pF, PMMCOREV = 3
1.8 V
-10
3V
-8
2.4 V
-10
3V
-8
MAX
f_SYSTEM
20
18
16
15
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(USCI)} + t_SU,SI(Slave), t_SU,MI(USCI) + t_{VALID,SO(Slave)}).
For the slave's parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 11 and .
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in
Figure 11 and .
CKPL = 0
1/f_UCxCLK
UCLK
CKPL = 1
SOMI
t_LO/HI
t_LO/HI
t_SU,MI
t_HD,MI
SIMO
t_HD,MO
t_VALID,MO
Figure 11. SPI Master Mode, CKPH = 0
Copyright © 2010–2012, Texas Instruments Incorporated
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