THS3215 Datasheet, PDF (6/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
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Electrical Characteristics: D2S (continued)
at +V_CC = 6.0 V, –V_CC = –6.0 V, A_V = 2 V/V, 25-Ω source impedance, input common-mode voltage (V_IC) = 0.25 V, external
OPS input selected (PATHSEL ≥ 1.3 V), V_REF = GND, R_LOAD = 100 Ω, and T_J ≈ 25˚C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT LEVEL
(1)
OUTPUT ⁽⁶⁾
Output voltage headroom to either supply
Output current drive
DC output impedance
T_J ≈ 25°C
T_J = –40°C to +85°C
±0.8 V_PP, R_LOAD = 20 Ω
Load current = ±20 mA
1.4
1.5
1.75 V
A
1.95 V
B
±35
±45
mA
A
0.3
0.45 Ω
A
POWER SUPPLY (D2S + Midsupply Buffer Only; OPS Disabled: DISABLE pin ≥ 1.3 V)
Supply current
±6-V supplies
20.2
21.3
23 mA
A
Supply current temperature coefficient
8
µA/°C
C
Positive power-supply rejection ratio
(+PSRR)
Referred to input
62
71
dB
A
Negative power-supply rejection ratio
(–PSRR)
Referred to input
61
71
dB
A
(6) Output measured at pin 6.
7.6 Electrical Characteristics: OPS
at +V_CC = 6.0 V, –V_CC = –6.0 V, 25-Ω D2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF = GND,
R_F = 249 Ω⁽¹⁾, R_G = 162 Ω, A_V = 2.5 V/V, OPS R_LOAD = 100 Ω, OPS enabled (DISABLE ≤ 0.7 V or floated), external OPS input
selected (PATHSEL ≥ 1.3 V), and T_J ≈ 25˚C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT LEVEL
(2)
AC PERFORMANCE ⁽³⁾
Small-signal bandwidth (SSBW)
Large-signal bandwidth (LSBW)
Bandwidth for 0.2-dB flatness
Slew rate⁽⁴⁾
Overshoot and undershoot
Rise and fall time
Settling time to 0.1%
2nd-order harmonic distortion (HD2)
3rd-order harmonic distortion (HD3)
Noninverting input voltage noise
V_OUT = 100 mV_PP, peaking < 2.0 dB
V_OUT = 5 V_PP
V_OUT = 5 V_PP
V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
Input t_r = 1 ns, V_OUT = 5-V step
f = 20 MHz, V_OUT= 5 V_PP
f = 20 MHz, V_OUT= 5 V_PP
f > 200 kHz
700
270
110
3000
4%
1.7
25
–66
–68
2.7
MHz
C
MHz
C
MHz
C
V/µs
C
C
ns
C
ns
C
dBc
C
dBc
C
nV/√Hz
C
Noninverting input current noise
f > 200 kHz
1.3
pA/√Hz
C
Inverting input current noise
f > 200 kHz
18
pA/√Hz
C
Closed-loop ac output impedance
f = 20 MHz
0.25
Ω
C
(1) Output power stage includes an internal 18.5-kΩ feedback resistor. This internal resistor, in parallel with an external 249-Ω R_F and 162-
Ω R_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.
(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈ T_J≈ 25°C; over temperature limits by
characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for
information. DC limits tested with no self-heating. Add internal self heating to T_A for T_J.
(3) Output measured at pin 11.
(4) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π × f_–3dB.
6
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