THS3215 Datasheet, PDF (34/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
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Feature Description (continued)
The gain from VREF to VO1 is shown in Equation 6:
V_REF
R1
§
¨¹
R1 R2 _©
R_F
·
¸
R_{G ¹}
V_O1
(6)
Getting both R1 and (R1 + R2) in terms of R_G and the target attenuation, α simplifies, as shown in Equation 7:
R1
R1 R2
R_G
1
1
D
D
R_G
1
1
D
1D
(7)
Putting Equation 7 back into the gain expression (Equation 6), and expanding out gives:
V_REF 1
D
§
¨¹
©
R_F
·
¸
R_{G ¹}
V_O1
(8)
Substituting the value of α from Equation 5 into Equation 8 reduces the expression to V_O1 = V_REF, a gain of 1
V/V. This gain is very precise, as shown in the D2S Electrical Characteristics table, where the tested dc limits are
0.985 V/V to 1.015 V/V.
The D2S output offset and drift are largely determined by the internal elements. The only external consideration
is the dc source impedance at the two buffer inputs. With low source impedance, the D2S output offset is tested
to be within ±35 mV, that becomes a maximum ±17 mV input differential offset specification. Assuming the dc
source impedances are closely matched, the mismatch in the two input bias currents adds another input offset
term for higher source impedances. The input bias offset current is limited in test to be < ±0.40 µA. This error
term does not rise to add more than ±1 mV input differential offset until the dc source impedance exceeds 2.5
kΩ. A high dc source impedance most commonly occurs in an input ac-coupled, single-supply application, where
dc offsets are less critical.
The absolute input bias currents modify the common-mode input voltage if the dc source resistance is too large.
The input bias current is tested to a limit of ±4 µA on each input. In order to move the input common-mode
voltage by ±100 mV, the dc source impedance must exceed 25 kΩ. This added input common-mode voltage is
cancelled by the D2S at the output (pin 6) and is set to the reference voltage applied at VREF (pin 14).
The D2S output noise is largely fixed by the internal elements. The D2S shows a differential input voltage noise
of 6 nV/√Hz, and a current noise of 2 pA/√Hz on each input. Higher termination resistors increase this source
noise, as given by Equation 9, where R_t is the dc termination impedance at each buffer input. The D2S has a 1/f
corner at approximately 10 kHz (see Figure 18).
e_{i _ diff}
6 nV ² 2 4kTR_t 2 2 pA u R_t ²
(9)
The total differential input noise is dominated by the differential voltage noise. For instance, evaluating this
expression for R_t = 200 Ω on each input, increases the total differential input noise to 6.5 nV/√Hz, only slightly
greater than the 6 nV/√Hz for the D2S with 0-Ω source R_t on each input. If higher final output SNR is desired,
consider generating as much input swing as the DAC can support by increasing the termination impedance. It is
possible that a lower tail current with higher R_t can yield improved SNR at the D2S input. This differential input
noise appears at the D2S output times a gain of 2 V/V.
e_{out _ diff} 2 u e_{i _ diff}
(10)
9.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)
This optional block can be completely unconnected and not used if the design does not require this feature.
Internal 50-kΩ resistors to the power supplies bias the input of the buffer to the midpoint of the supplies used.
The internal resistors set a midsupply operating point when the buffer is not used, as well as a default midsupply
point at the buffer output to be used in other stages for single-supply, ac-coupled applications.
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