THS3215 Datasheet, PDF (41/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

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THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
Using the OPS to receive and amplify a signal in the inverting mode with a matched terminating impedance
requires another resistor to ground (R_M) along with R_G. This R_M resistor is shown in Figure 85 for a 50-Ω
matched input impedance design.
50-Ÿ
Source
VIN-
12
RG
RF
RM
OPS
Stage
6
From D2S
VIN+ 9
11 VOUT
+
Figure 85. Inverting OPS Operation With Matched Input Impedance
Table 3 gives the recommended external resistor values versus gain for the inverting gain mode with input
matching configuration. Table 3 solves for the required R_F to simultaneously allow the gain, input impedance (50
Ω), and feedback transimpedance to be set to the optimal target values. The table includes the effect of the
internal 18.5-kΩ feedback resistor, and minimizes the RMS error to input impedance target (Z_I) and overall gain.
TARGET
GAIN
—(V/V)
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Table 3. Resistor Values Versus Gain for the Inverting OPS Configuration
MEASURED
SSBW
(MHz)
700
—
—
700
—
—
—
—
570
—
—
—
—
—
—
—
—
—
175
BEST
R_F (Ω)
294
267
237
226
215
210
205
226
249
274
301
324
348
374
402
422
449
475
499
BEST
R_G (Ω)
287
174
118
88.7
71.5
59
51.1
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
BEST
R_M (Ω)
60.4
69.8
86.6
113
169
316
1910
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
CALCULATED GAIN
—(V/V)
1.008
1.533
2.009
2.543
3.017
3.553
4.006
4.529
4.990
5.491
6.032
6.493
6.974
7.495
8.056
8.457
8.998
9.519
10.000
(dB)
0.072
3.712
6.061
8.106
9.592
11.011
12.055
13.120
13.962
14.793
15.609
16.249
16.870
17.495
18.122
18.544
19.083
19.572
20.000
GAIN ERROR
(%)
0.835
2.213
0.469
1.705
0.577
1.508
0.161
0.645
-0.201
-0.164
0424
-0.108
-0.372
-0.067
0.701
-0.507
-0.023
0.200
0.000
Z_I (Ω)
49.90
49.82
49.95
49.69
50.24
49.72
49.77
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
49.90
Z_I ERROR
(%)
-0.003
-0.168
0.091
-0.415
0.688
-0.366
-0.264
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
–0.200
At higher gains, R_M increases to larger values, and the resistor is excluded from the circuit. The resulting input
impedance of the network is resistor R_G. From that point, R_F simply increases to get higher gains, thereby rapidly
reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in Table 3
holds a more constant SSBW versus the noninverting mode (see Figure 26).
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