THS3215 Datasheet, PDF (57/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

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10.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver
VMID_OUT
15 V
10 nF
49.9
VMID_OUT
49.9
10 nF
16
15
50 k
1 …F
1
50 k
1.62 k
2 x1
2 VPP
x1
50
+
1.62 k
250
500
3 x1
14
100
VPATHSEL=15 V
4
THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
15 V
13
18.5 k
VMID_OUT
75
12
OPS AV = 3.4 V/V
182
5.9
11
VOUT = 12 VPP
220 pF
10
18.5 k
(VMID_OUT + 3.5 VPP)
9
5
6
7
8
VO1 = VMID_OUT + 4 VPP
105
390 nH
15-MHz, 2nd-order Chebyshev
filter (0.2 dB ripple)
68 pF
10
825
1 …F
Figure 103. Single-Supply, Heavy Capacitive-Load Driving
10.1.1.3.1 Detailed Design Procedure
The very-high peak output current and slew rate of the THS3215 OPS make it particularly suitable for driving
heavy capacitive loads, such as the piezo elements used in continuous wave (CW) applications that require high-
amplitude, sinusoidal-type excitations. The driver is quickly disabled during the receive time when the output
transmit and receive switch is moved to receive mode. Figure 103 shows an example design using the internal
midscale buffer to bias all the stages to midsupply on a single 15-V design. There are many elements to this
example that also apply to any single-supply application. The key points here are:
1. The differential DAC input signal is ac-coupled to the D2S input, and the termination resistors are scaled up
and biased to midsupply using the output of the midscale buffer, VMID_OUT (pin 15). The 10-nF blocking
capacitors before the 1.62 kΩ termination resistors set the high-pass pole at 10 kHz.
2. The internal divider resistors of the midscale buffer are decoupled using a 1-µF capacitor on VMID_IN (pin
1). Use of the capacitor improves both noise and PSRR through the reference buffer stage. In turn, the noise
injected by the bias source is reduced at the various places the buffer output is used.
3. V_{MID_OUT} is also applied to the VREF input (pin 14) to hold the D2S output centered on the single 15-V
supply. There is minimal dc current into VREF because the D2S input buffers operate at the same common-
mode voltage, V_{MID_OUT}.
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