THS3215 Datasheet, PDF (42/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
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9.3.3.1 Output DC Offset and Drift for the OPS
The OPS provides modest dc precision with typical, minimum, and maximum dc error terms in Table 4. The input
offset voltage applies to either input path with very little difference between the internal and external paths.
Table 4. Typical Offset and Bias Current Values for the OPS
PARAMETER
V_IO
I_bn
I_bi
TYPICAL
±1
5
±5
MINIMUM
–15
–5
–35
MAXIMUM
15
15
35
UNIT
mV
µA
µA
Selecting the internal path results in no source resistance for I_bn, so that term drops out. When the external path
is selected, a dc source impedance may be present, so the I_bn term creates another error term, and adds to the
total output offset.
Stepping through an example design for the OPS output dc offset using the external path with a low insertion
loss filter shown in Figure 92, along with its R_F and R_G values, gives the following results:
• R_S for the I_bn term = 90.9 Ω || 464Ω = 76 Ω. (dc source impedance for the filter design)
• R_F including the internal 18.5 kΩ resistor = 205 Ω || 18.5 kΩ = 202.7 Ω
• Resulting gain with the 102-Ω R_G element = 2.99 V/V
Table 5 shows the typical and worst-case output error terms. Note that a positive current out of the noninverting
input gives a positive output offset term, whereas a positive current out of the inverting input gives a negative
output term.
Table 5. Output Offset Voltage Contribution From Various Error Terms at 25°C
ERROR TERM
I_bn × R_S × A_V
V_IO × A_V
I_bi × R_F
Total error
TYPICAL
1.136
±2.99
±1.014
–2.87 to +5.14
MINIMUM
–1.136
–44.85
–7.095
–53.08
MAXIMUM
3.408
44.85
7.095
55.35
UNIT
mV
mV
mV
mV
The input offset voltage dominates the error terms. The worst-case numbers are calculated by adding the
individual errors algebraically, but is rarely seen in practice. None of the OPS input dc error terms are correlated.
To compute output drift numbers, use the same gains shown in Table 5 with the specified drift numbers.
The OPS PATHSEL control responds extremely quickly with low-switching glitches, as shown in Figure 86. For
this test, the D2S input is set to GND, and the output of the D2S is connected to the external OPS input. The
PATHSEL switch is then toggled at 10 MHz. The results show the offset between the internal and external paths
as well matched.
3
0.12
2
0.08
1
0.04
0
0
-1
-0.04
-2
PATHSEL In
OPS V_OUT
-3
Time (20 ns/div)
-0.08
-0.12
D505
Figure 86. OPS Path-Select Switching Glitch
42
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