THS3215 Datasheet, PDF (46/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
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9.3.4 Digital Control Lines
The THS3215 provides two logic input lines that control the input path to the OPS and the OPS power disable
feature; both are referenced to GND (pin 7). The control logic defaults to a logic-low state when the pins are
externally floated. The GND pin must have a dc path to some reference voltage for correct operation. Float the
two logic control lines to enable the OPS and select the internal path connecting the D2S internal output to the
OPS noninverting input. Figure 89 shows a simplified internal schematic for either logic control input pin.
+VCC
50 PA
20 PA
Logic
1k
Control
Q1
Input
19 k
VCTRL
100
Q2
Q3
D1
D2
17.5 k
D3
PIN 7
Figure 89. Logic Control Internal Schematic
The Q2 branch of the differential pair sets up a switch threshold approximately 1 V greater than the voltage
applied to the GND pin. If the control input is floating or < 0.7 V, the differential-pair tail current diverts to the 100-
Ω detector load, and results in an output voltage (V_CTRL, shown in Figure 89) that activates the desired mode.
The floated pin default voltage is the PNP base current into the 19-kΩ resistor. As the control pin voltage rises
above 1.3 V, the differential-pair current is completely diverted away from the 100-Ω side, thus switching states.
This unique design allows the logic control inputs to be connected to a single-supply as high as 15.9 V, in order
to hold the inputs permanently high, while still accepting a low ground-referenced logic swing for single-supply
operation. The NPN transistor (Q3) and two diodes (D1 and D2) act as a clamp to prevent large voltages from
appearing across the differential stage.
When the OPS is disabled, both input paths to the OPS are also opened up regardless of the state of PATHSEL
(pin 4).
9.4 Device Functional Modes
Any combination of the three internal blocks can be used separately, or in various combinations. The following
sections describe the various functional modes of the THS3215.
9.4.1 Full-Signal Path Mode
The full-signal path from the D2S to the OPS is available in various options. Three options are described in the
following subsections.
9.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage
The most basic operation is to ground VREF (pin 14), and use the internal connection from the D2S to the OPS
to provide a differential to single-ended, high-power driver. Figure 90 shows the characterization circuit used for
the combined performance specifications.
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