THS3215 Datasheet, PDF (45/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

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THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
9.3.3.4 Driving Capacitive Loads
The OPS can drive heavy capacitive loads very well, as shown in Figure 43 to Figure 48. All high-speed
amplifiers benefit from the addition of an external series resistor to isolate the load capacitor from the feedback
loop. Not using a series isolation resistor often leads to response peaking and possibly oscillation. If frequency
response flatness under capacitive load is the design goal, use slightly higher R_F values at the lower gains.
Target a slightly-higher feedback transimpedance to increase the nominal phase margin before the capacitive
load acts to decrease it. Using a higher R_F value increases the frequency response flatness across a range of
capacitive loads using lower external series resistor values. Although the suggested R_F and R_G values of Table 1
apply when driving a 100-Ω load, if the intended load is capacitive (for example, a passive filter with a shunt
capacitor as the first element, another amplifier, or a Piezo element), use the values reported in Table 6 as a
starting point. The values in Table 6 were used to generate Figure 43 and Figure 44. The results come from a
nominal total feedback transimpedance target of 405 Ω (versus 351 Ω used for Table 3), and includes the
internal 18.5-kΩ resistor in the design. Table 6 finds the least error to target gain in the selection of standard
resistor values, and limits the minimum R_G to 20 Ω. The gains calculated here put 18.5-kΩ in parallel with the
reported external standard value R_F.
TARGET GAIN
(V/V)
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
Table 6. Suggested R_F and R_G Over Gain When Driving a Capacitive Load
BEST R_F
(Ω)
487
BEST R_G (Ω)
953
CALCULATED GAIN
(V/V)
(dB)
1.494
3.488
GAIN ERROR
(%)
–0..389
432
422
1.995
6
–0.233
402
261
2.501
7.963
0.048
332
162
3.006
9.559
0.191
274
107
3.515
10.917
0.416
221
73.2
3.974
11.984
–0.662
165
46.4
4.513
13.090
0.295
158
39.2
4.984
13.952
–0.320
165
36.5
5.467
14.755
–0.602
169
33.2
6.029
15.605
0.486
169
30.1
6.547
16.321
0.729
174
28.7
6.989
16.888
–0.161
174
26.7
7.437
17.429
–0.833
178
24.9
8.060
18.127
0.753
178
23.2
8.578
18.668
0.915
178
22.1
8.955
19.041
–0.499
182
21
9.558
19.608
0.613
187
20.5
10.006
20.005
0.056
As the capacitive load or amplifier gain increases, the series resistor values can be reduced to hold a flat
response (see Figure 43). See Figure 44 for the measured SSBW shapes for various capacitive loads configured
with the suggested series resistor from the output of the OPS and the R_F and R_G values suggested in Table 6 for
a gain of 2.5 V/V. This measurement includes a 200-Ω shunt resistor in parallel with the capacitive load as a
measurement path.
Figure 45 and Figure 46 demonstrate the OPS harmonic distortion performance when driving a range of
capacitive loads. These figures show suitable performance for large-signal, piezo-driver applications. If voltage
swings higher than 12 V_PP are required, consider driving the OPS output into a step-up transformer. The high
peak-output current for the OPS supports very fast charging edge rates into heavy capacitive loads, as shown in
the step response plots (see Figure 47 and Figure 48). This peak current occurs near the center of the transition
time driving a capacitive load. Therefore, the I × R drop to the capacitive load through the series resistor is at a
maximum at midtransition, and 0 V at the extremes (low dV/dT points). For even better performance driving
heavy capacitive loads, consider using the THS3217, a DAC output amplifier with higher output current and slew
rate.
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