THS3215 Datasheet, PDF (33/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

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THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
Feature Description (continued)
This analysis for matched gains and buffer loads can be applied to a more general, discrete design using
different target gains and starting R_F values. It is clearly useful to have the attenuation and buffer loading
accurately controlled. Therefore, it is very important to control the impedance at VREF (pin 14) to be as low as
possible. For instance, using the midscale buffer to drive VREF only adds 0.21-Ω dc impedance in series with
R2. This low, dc output impedance can only be delivered with a closed-loop buffer design. For discrete
implementations of this D2S, consider the BUF602 buffer and LMH6702 wideband CFA. For even better dc and
ac output impedance in the buffers (and possibly better gain), use a closed-loop, dual, wideband op amp like the
OPA2889 for lower frequency applications, or the OPA2822 for higher frequency. These unity gain stable op
amps can be used as buffers, offering different performance options along with the LMH6702 wideband CFA
over the design point chosen for the THS3215.
After gain matching is achieved in the single op amp differential stage, the common-mode input voltage is
cancelled to the output, and the VREF input voltage is amplified by 1 V/V to the output. The analysis circuit is
shown in Figure 78, where VREF is shown grounded at the R2 element.
RG
250
RF
500
VCM
VO1
+
R1
50
R2
100
Figure 78. D2S Common-Mode Cancellation
The gain magnitudes are equal on each side of the differential inputs; therefore, the common-mode inputs
achieve the same gain magnitude, but opposite phase, resulting in common-mode signal cancellation. The
inverting path gain is V_CM × (R_F / R_G). The noninverting path gain is V_CM × α × (1 + R_F / R_G). Using Equation 5:
R_F
D
R_G
§
¨¹
R_F
·
¸
© ^RG ¹
(5)
the noninverting path gain becomes +V_CM × R_F / R_G, and adding that result to the inverting path signal cancels
the input common-mode voltage to zero. Slight gain mismatches reduce this rejection to the 48-dB typical
CMRR, with a 42-dB tested minimum. The 42-dB minimum over the 3-V maximum common-mode input range
adds another ±23.8-mV worst-case D2S output offset term to the specified maximum ±35-mV output offset with
0-V input common-mode voltage. The polarity of the gain mismatch is random.
The VREF pin input voltage (V_REF) generates a gain of 1 V/V using the analysis shown in Figure 79.
RG
250
RF
500
VO1
+
R1
50
R2
100
VREF
Figure 79. Gain Transfer Function from VREF to VO1
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