THS3215 Datasheet, PDF (28/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
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8.8 Midscale Buffer R_OUT Versus C_LOAD Measurement
For the tests in Figure 53 and Figure 54, the circuit shown in Figure 75 was used. The 150-Ω load circuit
configured as shown, provides a 50-Ω path from the network analyzer back to the output of the buffer. As shown
in Figure 75, place R_OUT below the load capacitor to improve the phase margin of the closed-loop buffer output,
while adding 0-Ω dc impedance into the line connecting VMID_OUT (pin 15) to the VREF pin. When using the
midscale buffer to drive the VREF input, use a decoupling capacitor at VMID_OUT to reduce broadband noise
and source impedance.
Network
Analyzer
GND Port 1
50
Port 2
50
+VCC2
16
150Ÿ
Load
50 k
VMID_IN
1
VMID_OUT
118
x1
15
49.9
50 k
CLOAD
88.7
ROUT
5
-VCC2
Figure 75. R_OUT Versus C_LOAD Measurement Circuit
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