THS3215 Datasheet, PDF (43/71 Pages) Texas Instruments – THS3215 650-MHz, Differential to Single-Ended DAC Output Amplifier

www.ti.com
THS3215
SBOS780A – MARCH 2016 – REVISED APRIL 2016
The OPS includes a disable feature that reduces power consumption from approximately 11 mA to 2 mA. The
logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference
(GND, pin 7) is normally grounded and also provides a connection to the internal 18.5-kΩ resistor on VIN+ (pin 9,
default bias to pin 7). Operating in a single-supply configuration with –V_CC at GND and the external OPS input
(VIN+) floated, places VIN+ internally at –V_CC = GND. Driving the external OPS input (VIN+) from a source within
the operating range overrides the bias to –V_CC. However, if the application requires VIN+ to be floated in a
single-supply operation, consider centering the voltage on VIN+ with an added 18.5-kΩ external resistor to the
+V_CC supply.
If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled
state. Increasing the voltage on the DISABLE pin to greater than 1.3 V disables the OPS and reduces the current
to approximately 2 mA. In a single-supply design, the OPS can be disabled by setting DISABLE to +V_CC, even up
to the maximum operating supply of 15.8 V.
Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level
is required, and GND (pin 7) is biased to a different voltage, be sure the source can sink the typical 280 µA
coming out of GND. Also recognize that the 18.5-kΩ bias resistor on the external OPS input (VIN+) is connected
to GND voltage internally.
As shown in Figure 56, the OPS enables in approximately 100 ns from the logic threshold at 1.0 V, while
disabling to a final value in approximately 500 ns.
9.3.3.2 OPS Harmonic Distortion (HD) Performance
The OPS in the THS3215 provides one of the best HD solutions available through high power levels and
frequencies. Figure 31 and Figure 32 show the swept-frequency HD2 and HD3, where the second harmonic is
clearly the dominant term over the third harmonic. Typical wideband CFA distortion is reported only through 2-
V_PP output, while Figure 31 and Figure 32 provide sweeps at 5 V_PP and 8 V_PP into a 100-Ω load. These curves
show an approximate 20-dB per decade rise with frequency due to loop-gain roll-off.
The distortion performance is extremely robust as a function of load resistance (see Figure 33 and Figure 34).
Normally, heavier loads degrade the distortion performance, as shown by the HD2 in Figure 33. However at
frequencies greater than 30 MHz, the HD2 actually improves slightly as the output load is increased from 500 Ω
to 100 Ω.
One of the key advantages offered by the CFA design in the OPS is that the distortion performance holds
approximately constant over gain, as seen in the full-path distortion measurements of Figure 9 and Figure 10.
Here, the D2S provides a fixed gain of 2 V/V driving a 200-Ω interstage load and using the internal path to drive
the OPS at gains from 1.5 V/V to 10 V/V. Hold the loop-gain approximately constant by adjusting the feedback
R_F value with gain to achieve vastly improved performance versus a voltage-feedback-based design.
Testing a 5-V_PP output from the OPS with the supplies swept from the minimum ±4 V to ±7.5 V in Figure 35 and
Figure 36 show:
1. The 1.5-V headroom on ±4-V supplies and ±2.5-V output voltage results in degraded performance. At the
lower supplies, target lower output swings for improved linearity performance.
2. The HD2 does not change significantly with supply voltages above ±6 V. The HD3 does improve slightly at
higher supply-voltage settings.
From these plots at ±7.5-V supplies, a 5-V_PP output into 100-Ω load shows better than –60-dBc HD2 and HD3
performance through 30 MHz. This exceptional performance is available with the OPS configured as a
standalone amplifier. Combining the standalone OPS performance with the D2S (see Figure 3 and Figure 4)
does not degrade the full, signal-path distortion levels. With the D2S and OPS running together at a final 5-V_PP
output and 30 MHz, the HD2 changes to –63 dBc and HD3 changes to –59 dBc on ±6-V supplies. Lower output
swings for the combined stages provide much lower distortion. The 2-V_PP output curves on Figure 3 and Figure 4
show –61 dBc for HD2 and HD3 at 50 MHz.
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: THS3215
Submit Documentation Feedback
43