DS92LV0421_15 Datasheet, PDF (6/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
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DS92LV0422 PIN DESCRIPTIONS
Pin Name Pin No.
I/O, Type
Description
Channel Link II Serial Interface
RIN++
40
I, CML True Input.
The output must be AC Coupled with a 0.1 μF capacitor.
RIN-
41
I, CML Inverting Input.
The output must be AC Coupled with a 0.1 μF capacitor.
Channel Link Parallel Output Interface
RxIN[3:0]+
15, 19, 21,
23
O, LVDS True LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
RxIN[3:0]-
16, 20, 22,
24
O, LVDS Inverting LVDS Data Output
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN+
17
O, LVDS True LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN-
18
O, LVDS Inverting LVDS Clock Output
This pair should have a 100 Ω termination for standard LVDS levels.
LVCMOS Outputs
LOCK
27
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is locked, output stated determined by OEN.
LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN.
See Table 5.
Control and Configuration
PDB
1
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
33
I, LVCMOS Parallel LVDS Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ)
VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ)
OEN
30
I, LVCMOS Output Enable.
w/ pull-down See Table 5.
OSS_SEL
35
I, LVCMOS Output Sleep State Select Input.
w/ pull-down See Table 5.
LFMODE
36
I, LVCMOS SSCG Low Frequency Mode — Pin or Register Control
w/ pull-down LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz)
LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz)
SSCG not avaialble above 65 MHz.
MAPSEL
34
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on TxOUT3+/-. See Figure 24
MAPSEL = 0, LSB on TxOUT3+/-. See Figure 23
CONFIG[1:0]
11, 10
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Limited Register Control
Determine the device operating mode and interfacing device. See Table 1
CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421
CONFIG [1:0] = 11: Interfacing to DS90C124
SSC[2:0]
7, 3, 2
I, LVCMOS Spread Spectrum Clock Generation (SSCG) Range Select
w/ pull-down See Table 8 and Table 9
RES
37
I, LVCMOS Reserved
w/ pull-down
Control and Configuration — STRAP PIN
EQ
28 [PASS]
STRAP EQ Gain Control of Channel Link II Serial Input
I, LVCMOS EQ = 1, EQ gain is enabled (~13 dB)
w/ pull-down EQ = 0, EQ gain is disabled (~1.625 dB)
6
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