DS92LV0421_15 Datasheet, PDF (37/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
www.ti.com
SNLS325C – MAY 2010 – REVISED APRIL 2013
1.8V
C11
C8
FB1
C3
FB2
C4
FB3
C5
DS92LV0422
VDDL
VDDTX
VDDL
VDDA
VDDA
VDDIO
VDDP
VDDSC
FB4
3.3V
C6
C9
C12
FB5
VDDIO
C7
C10
C13
VDDSC
TxCLKOUT+
Serial
Channel Link II
Interface
TxCLKOUT-
C1
TxOUT3+
RIN+
TxOUT3-
TxOUT2+
RIN-
C2
CMF
C15
TxOUT2-
TxOUT1+
TxOUT1-
TxOUT0+
Host
Control
BISTEN
PDB
R
C14
TxOUT0-
LOCK
PASS
1.8V
10k
RID
C1 - C2 = 0.1 PF (50 WV)
C3 ± C10 = 0.1 PF
C11 - C13 = 4.7 PF
C14, C15 = >10 PF
R = 10 k:
RID (See ID[x] Resistor Value Table)
FB1 - FB5: Impedance = 1 k:
Low DC resistance ( <1:)
ID[X]
SCL
SDA
RES
8 _GND
DAP (GND)
OEN
OSS_SEL
LFMODE
VODSEL
MAPSEL
CONFIG1
CONFIG0
SSC[2]
SSC[1]
SSC[0]
Figure 35. DS92LV0422 Typical Connection Diagram
Channel
Link
Interface
Power Up Requirements and PDB Pin
The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms
then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to V_DDIO, it is recommended to use a 10 kΩ pull-up and
a 22 uF cap to GND to delay the PDB input signal.
Transmission Media
The DS92LV0421 and the companion deserializer chipset is intended to be used in a point-to-point configuration,
through a PCB trace, or through twisted pair cable. The DS92LV0421 provide internal terminations providing a
clean signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms.
Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
Shielded or un-shielded cables may be used depending upon the noise environment and application
requirements.
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