DS92LV0421_15 Datasheet, PDF (12/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
www.ti.com
Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
DS92LV0422 CHANNEL LINK PARALLEL LVDS OUTPUT
t_LHT
t_THLT
t_DCCJ
Low to High Transition Time
High to Low Transition Time
Cycle-to-Cycle Output Jitter⁽¹⁾
R_L = 100Ω
TxCLKOUT± = 10 MHz
TxCLKOUT± = 75MHz
t_TTP1
t_TTP0
t_TTP6
t_TTP5
t_TTP4
t_TTP3
t_TTP2
t_DD
t_TPDD
LVDS Transmitter Pulse Position for bit 1
LVDS Transmitter Pulse Position for bit 0
LVDS Transmitter Pulse Position for bit 6
LVDS Transmitter Pulse Position for bit 5
LVDS Transmitter Pulse Position for bit 4
LVDS Transmitter Pulse Position for bit 3
LVDS Transmitter Pulse Position for bit 2
Delay-Latency
Power Down Delay
Active to OFF
10 – 75 MHz
75 MHz
t_TXZR
Enable Delay
OFF to Active
75 MHz
DS92LV0421 Channel Link II CML OUTPUT
t_HLT
Output Low-to-High Transition Time
See Figure 6
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 0
100
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
100
t_HLT
Output High-to-Low Transition Time
See Figure 7
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 0
130
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
100
t_XZD
Ouput Active to OFF Delay, SeeFigure 12
t_PLD
PLL Lock Time, See Figure 10⁽³⁾
R_L = 100Ω
t_SD
Delay - Latency, See Figure 13
R_L = 100Ω
t_DJIT
Output Total Jitter,
See Figure 15
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern
λ_STXBW Jitter Transfer
Function -3 dB Bandwidth
RxCLKIN = 43 MHz
RxCLKIN = 75 MHz
δ_STX
Jitter Transfer
Function Peaking
RxCLKIN = 43 MHz
RxCLKIN = 75 MHz
DS92LV0422 CHANNEL LINK II CML INPUT
t_DDLT Lock Time
SSCG = OFF,
10 MHz
SSCG = ON,
10 MHz
SSCG = OFF,
75 MHz
SSCG = ON,
65 MHz
t_DJIT
Input Jitter Tolerance
EQ = OFF
Jitter Frequency > 10 MHz
Typ Max
0.3
0.3
900
75
0
1
2
3
4
5
6
142*T
6
0.6
0.6
2100
125
143*T
10
40
55
200
300
200
300
260
390
200
5
1.5
147*T
0.3
2.2
3
1
1
300
15
10
148*T
7
14
6
8
>0.45
(1) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.
(2) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
(3) t_PLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN.
Units
ns
ns
ps
ps
UI ⁽²⁾
UI
UI
UI
UI
UI
UI
ns
ns
ns
ps
ps
ps
ps
ns
ms
ns
UI
MHz
MHz
dB
dB
ms
ms
ms
ms
UI
12
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