DS92LV0421_15 Datasheet, PDF (35/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
www.ti.com
SNLS325C – MAY 2010 – REVISED APRIL 2013
Table 13. DS92LV0422 DESERIALIZER — Serial Bus Control Registers (continued)
ADD ADD
(dec) (hex)
Register Name
Bit(s)
R/W
Default
(bin)
Function
3
3 Des Features 2
7:5
R/W
000 EQ Gain
4
R/W
0
EQ Enable
3
R/W
0
Reserved
2:0
R/W
000 SSC
Description
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
0: EQ = disabled
1: EQ = enabled
Reserved
IF LFMODE = 0 then:
000: SSCG OFF
001: fdev = ±0.9%, fmod = CLK/2168
010: fdev = ±1.2%, fmod = CLK/2168
011: fdev = ±1.9%, fmod = CLK/2168
100: fdev = ±2.3%, fmod = CLK/2168
101: fdev = ±0.7%, fmod = CLK/21300
110: fdev = ±1.3%, fmod = CLK/1300
111: fdev = ±1.57%, fmod = CLK/1300
IF LFMODE = 1, then:
001: fdev = ±0.7%, fmod = CLK/625
010: fdev = ±1.3%, fmod = CLK/625
011: fdev = ±1.8%, fmod = CLK/625
100: fdev = ±2.2%, fmod = CLK/625
101: fdev = ±0.7%, fmod = CLK/385
110: fdev = ±1.2%, fmod = CLK/385
111: fdev = ±1.7%, fmod = CLK/385
Applications Information
DISPLAY APPLICATION
The DS92LV0421 and DS92LV0422 chipset is intended for interface between a host (graphics processor) and a
Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. In a RGB888
application, 24 color bits (R[7:0], G[7:0], B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) are
supported across the serial link with PCLK rates from 10 to 75 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose signals may also be sent from host to display.
DS92LV0421 TYPICAL APPLICATION CONNECTION
Figure 34 shows a typical application of the DS92LV0421 for a 75 MHz 24-bit Color Display Application. The
LVDS inputs require external 100 ohm differential termination resistors. The CML outputs require 0.1 μF AC
coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors are placed near
the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be used for local
device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN pins. The
application assumes the companion deserializer (DS92LV0422) therefore the configuration pins are also both
tied Low. In this example the cable is long, therefore the VODSEL pin is tied High and a De-Emphasis value is
selected by the resistor R1. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is
connected also to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA
and ID[x] pins are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until
power is stable. Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power
lines for effective noise suppression.
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