DS92LV0421_15 Datasheet, PDF(29/48 Page) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421_15 Datasheet, PDF (29/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421, DS92LV0422

SNLS325C â MAY 2010 â REVISED APRIL 2013

Frequency

FPCLK+

FPCLK

FPCLK-

fdev(max)

1/fmod

Figure 27. SSCG Waveform

fdev(min)

Time

Power Saving Features

Des â Power Down Feature (PDB)

The DS92LV0422 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the

host and is used to save power, disabling the Des when the display is not needed. An auto detect mode is also

available. In this mode, the PDB pin is tied HIGH and the Des will enter POWER DOWN when the serial stream

stops. When the serial stream starts up again, the Des will lock to the input stream and assert the LOCK pin and

output valid data. In the POWER DOWN mode, the LVDS data and clock output states are determined by the

OSS_SEL status. Note â in POWER DOWN, the optional Serial Bus Control Registers are RESET.

Des â Stop Stream SLEEPFeature

The DS92LV0422 will enter a low power SLEEP state when the input serial stream is stopped. A STOP condition

is detected when the embedded clock bits are not present. When the serial stream starts again, the Des will then

lock to the incoming signal and recover the data. Note â in STOP CLOCK SLEEP, the optional Serial Bus

Control Registers values are RETAINED.

1.8V or 3.3V VDDIO Operation

The DS92LV0422 parallel control bus can operate with 1.8 V or 3.3 V levels (VDDIO) for host compatibility. The

1.8 V levels will offer a system power savings.

Built In Self Test (BIST)

An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is

useful in the prototype stage, equipment production, in-system test and also for system diagnostics. In the BIST

mode only a input clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a

test pattern (PRBS7) and drives the link at speed. The Des detects the PRBS7 pattern and monitors it for errors.

A PASS output pin toggles to flag any payloads that are received with 1 to 24 errors. Upon completion of the

test, the result of the test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS

indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration

of the test is controlled by the pulse width applied to the Des BISTEN pin.

Inter-operability is supported between this Channel Link II device and all Channel Link II generations (Gen

1/2/3) â see respective datasheets for details on entering BIST mode and control.

Sample BIST Sequence

See Figure 28 for the BIST mode flow diagram.

Step 1: Place the serializer in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled via the

BISTEN pin. An RxCLKIN is required for all the Ser options. When the deserializer detects the BIST mode

pattern and command the parallel data and control signal outputs are shut off.

Step 2: Place the deserializer in BIST mode by setting the BISTEN = H. The Des is now in the BIST mode and

checks the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will

switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted

to determine the payload error rate.

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Product Folder Links: DS92LV0421 DS92LV0422

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