DS92LV0421_15 Datasheet, PDF (4/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
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DS92LV0421 PIN DESCRIPTIONS
Pin Name Pin No.
I/O, Type
Description
Channel Link Parallel Input Interface
RxIN[3:0]+
2, 33, 31,
29
I, LVDS
True LVDS Data Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxIN[3:0]-
1, 34, 32,
30, 28
I, LVDS
Inverting LVDS Data Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN+
35
I, LVDS True LVDS Clock Input
This pair should have a 100 Ω termination for standard LVDS levels.
RxCLKIN-
34
I, LVDS Inverting LVDS Clock Input
This pair should have a 100 Ω termination for standard LVDS levels.
Control and Configuration
PDB
23
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Device is enabled (normal operation).
Refer to Power Up Requirements and PDB Pin
PDB = 0, Device is powered down
When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
20
I, LVCMOS Differential Driver Output Voltage Select — Pin or Register Control
w/ pull-down VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications
VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ)
De-Emph
19
I, Analog De-Emphasis Control — Pin or Register Control
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4
MAPSEL
26
I, LVCMOS Channel Link Map Select — Pin or Register Control
w/ pull-down MAPSEL = 1, MSB on RxIN3+/-. See Figure 24
MAPSEL = 0, LSB on RxIN3+/-. See Figure 23
CONFIG[1:0]
10, 9
I, LVCMOS
w/ pull-down
Operating Modes — Pin or Limited Register Control
Determines the device operating mode and interfacing device. See Table 1
CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter
DISABLED
CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter
ENABLED
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124
CONFIG [1:0] = 11: Interfacing to DS90C124
ID[x]
4
I, Analog Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10
SCL
SDA
BISTEN
6
I, LVCMOS Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
7
I/O, LVCMOS Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor V_DDIO.
21
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES[7:0]
25, 3, 36, I, LVCMOS Reserved - tie LOW
27, 18, 13, w/ pull-down
12, 8
Channel Link II Serial Interface
DOUT+
16
O, CML True Output.
The output must be AC Coupled with a 0.1 μF capacitor.
DOUT-
15
O, CML Inverting Output.
The output must be AC Coupled with a 0.1 μF capacitor.
4
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