DS92LV0421_15 Datasheet, PDF (26/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
Power Saving Features
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Ser — Power Down Feature (PDB)
The DS92LV0421 has a PDB input pin to ENABLE or POWER DOWN the device. This pin is controlled by the
host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode,
the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – in POWER DOWN,
the optional Serial Bus Control Registers are RESET.
Ser — Stop Clock Feature
The DS92LV0421 will enter a low power SLEEP state when the RxCLKIN is stopped. A STOP condition is
detected when the input clock frequency is less than 3 MHz. The clock should be held at a static Low or high
state. When the RxCLKIN starts again, the device will then lock to the valid input RxCLKIN and then transmits
the RGB data to the desializer. Note – in STOP CLOCK SLEEP, the optional Serial Bus Control Registers values
are RETAINED.
1.8V or 3.3V VDDIO Operation
The DS92LV0421 parallel control bus can operate with 1.8 V or 3.3 V levels (V_DDIO) for host compatibility. The
1.8 V levels will offer a system power savings.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
Deserializer Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew rate select. The Des features power saving features
with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
Oscillator Output — Optional
The DS92LV0422 provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or through the registers.
CLOCK-DATA RECOVERY STATUS FLAC (LOCK), OUTPUT ENABLE (OEN) AND OUTPUT STATE
SELECT (SS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is LOW and the Channel Link
interface state is determined by the state of the OSS_SEL pin.
After the DS92LV0422 completes its lock sequence to the input serial data, the LOCK output is driven HIGH,
indicating valid data and clock recovered from the serial input is available on the Channel Link outputs. The
TxCLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to
the recovered clock (or vice versa). Note that the Channel Link outputs may be held in an inactive state (TRI-
STATE®) through the use of the Output Enable pin (OEN).
If there is a loss of clock from the input serial stream, LOCK is driven LOW and the state of the outputs are
based on the OSS_SEL setting (configuration pin or register).
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