DS92LV0421_15 Datasheet, PDF (36/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
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VDDIO
C10 C8
FB1
C3
DS92LV0421
VDDIO
VDDTX
VDDHS
C4
FB2
1.8V
C9 C11
Channel Link
Interface
LVDS
100 : Terminations
Host
Control
1.8V
10k
RID
RxCLKIN-
RxCLKIN+
RxIN3-
RxIN3+
RxIN2-
RxIN2+
RxIN1-
RxIN1+
RxIN0-
RxIN0+
ID[X]
SCL
SDA
BISTEN
PDB
R
C13
CONFIG1
CONFIG0
MAPSEL
VDDP
C12 C5
VDDL
C6
VDDRX
C7
DOUT+
DOUT-
FB3
FB4
FB5
C1
Serial
Channel Link II
Interface
C2
VODSEL
De-Emph
VDDIO
R1
RES7
RES6
RES5
RES4
RES3
RES2
RES1
RES0
DAP (GND)
NOTE:
C1-C2 = 0.1 PF (50 WV)
C3-C9 = 0.1 PF
C10-C12 = 4.7 PF
C13 = >10 PF
R = 10 k:
R1 (cable insertion loss specific)
RID (see ID[x] Resistor Value Table)
FB1-FB5: Impedance = 1 k:,
low DC resistance (<1:)
Figure 34. DS92LV0421 Typical Connection Diagram
DS92LV0422 TYPICAL APPLICATION CONNECTION
shows a typical application of the DS92LV0422 for a 75 MHz 24-bit Color Display Application. The CML inputs
require 0.1 μF AC coupling capacitors to the line. The line driver includes internal termination. Bypass capacitors
are placed near the power supply pins. At a minimum, four 0.1 µF capacitors and a 4.7 µF capacitor should be
used for local device bypassing. System GPO (General Purpose Output) signals control the PDB and BISTEN
pins. The application assumes the companion deserializer (DS92LV0422) therefore the configuration pins are
also both tied Low. The interface to the host is with 1.8 V LVCMOS levels, thus the VDDIO pin is connected also
to the 1.8V rail. The Optional Serial Bus Control is not used in this example, thus the SCL, SDA and ID[x] pins
are left open. A delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
Bypass capacitors are placed near the power supply pins. Ferrite beads are placed on the power lines for
effective noise suppression.
36
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