DS92LV0421_15 Datasheet, PDF (32/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
www.ti.com
SDA
SCL
S
START condition, or
START repeat condition
Figure 31. START and STOP Conditions
P
STOP condition
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after
every data byte is successfully received. When the master is reading data, the master ACKs after every data
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop
condition. A READ is shown in Figure 32 and a WRITE is shown in Figure 33.
If the Serial Bus is not required, the three pins may be left open (NC).
Resistor
RID kΩ
0.47
2.7
8.2
Open
Table 10. ID[x] Resistor Value – DS92LV0421
Address
7'b
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
Address
8'b
0 appended
(WRITE)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
Resistor
RID kΩ
0.47
2.7
8.2
Open
Table 11. ID[x] Resistor Value – DS92LV0422
Address
7'b
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
Address
8'b
0 appended
(WRITE)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
AA
21
A
0
1
c
k
Data
a
c
k
P
Figure 32. Serial Control Bus — READ
32
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