DS92LV0421_15 Datasheet, PDF(30/48 Page) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421_15 Datasheet, PDF (30/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421, DS92LV0422

SNLS325C â MAY 2010 â REVISED APRIL 2013

www.ti.com

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the

data and the final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If

there was one or more errors detected, the PASS output will be Low. The PASS output state is held until a new

BIST is run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of the

BISTEN signal.

Step 4: To return the link to normal operation, the ser and des BISTEN input are set Low. The Link returns to

normal operation.

Figure 29 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2

shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link

(differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting

the interconnect, reducing signal condition enhancements (De-Emphasis, VODSEL, or deserializer Equalization).

Normal

Step 1: SER in BIST

BIST

Wait

Step 2: Wait, DES in BIST

BIST

Start

Step 3: DES in Normal

Mode - check PASS

BIST

Stop

Step 4: SER in Normal

Figure 28. BIST Mode Flow Diagram

BER Calculations

It is possible to calculate the approximate Bit Error Rate (BER). The following is required:

â¢ Pixel Clock Frequency (MHz)

â¢ BIST Duration (seconds)

â¢ BIST test Result (PASS)

The BER is less than or equal to one over the product of 24 times the RxCLKIN rate times the test duration. If we

assume a 65MHz RxCLKIN, a 10 minute (600 second) test, and a PASS, the BERT is â¤ 1.07 X 10E-12

The BIST mode runs a check on the data payload bits. The LOCK pin also provides a link status. It the recovery

of the C0 and C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The

combination of the LOCK and At-Speed BIST PASS pin provides a powerful tool for system evaluation and

performance monitoring.

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