DS92LV0421_15 Datasheet, PDF (31/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
BISTEN
(DS90UR907Q)
BISTEN
(Deserializer)
TxCLKOUT
(Diff.)
TxOUT[3:0]
(Diff.)
DATA
(internal)
PASS
Prior Result
DATA
(internal)
PASS
Prior Result
Normal
PRBS
X = bit error(s)
X
X
X
BIST Test
BIST Duration
Figure 29. BIST Waveforms
PASS
FAIL
BIST
Result
Held
Normal
Optional Serial Bus Control
The DS92LV0421 and DS92LV0422 may be configured by the use of a serial control bus that is I2C protocol
compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap pins. A write
of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins. Multiple
devices may share the serial control bus since multiple addresses are supported. See Figure 30.
The serial bus is comprised of three pins. The SCL is a Serial Bus Clock Input. The SDA is the Serial Bus Data
Input / Output signal. Both SCL and SDA signals require an external pull up resistor to V_DDIO. For most
applications a 4.7 kΩ pull up resistor to 3.3V may be used. The resistor value may be adjusted for capacitive
loading and data rate requirements. The signals are either pulled High, or driven Low.
1.8V
HOST
SCL
SDA
3.3V
4.7k
4.7k
10k
ID[X]
R_ID
DS92LV0421/
DS92LV0422
SCL
SDA
To other
Devices
Figure 30. Serial Control Bus Connection
The third pin is the ID[X] pin. This pin sets one of five possible device addresses. Three different connections are
possible. The pin may be tied to ground. The pin may be pulled to V_DD (1.8V, NOT V_DDIO)) with a 10 kΩ resistor.
Or a 10 kΩ pull up resistor (to V_DD1.8V, NOT V_DDIO)) and a pull down resistor of the recommended value to set
other three possible addresses may be used. See Table 10.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when
SCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. See
Figure 31
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