DS92LV0421_15 Datasheet, PDF (23/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
RxCLKIN +/-
RxIN3 +/-
Previous cycle
RxIN2 +/-
Current cycle
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
R[6]
(bit 21)
B[2]
(bit 14)
RxIN1 +/-
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
RxIN0 +/-
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
Figure 24. 8–bit Channel Link Mapping: MSB's on RxIN3
R[1]
(bit 1)
R[0]
(bit 0)
Video Control Signal Filter
The three control bits can be used to communicate any low speed signal. The most common use for these bits is
in the display or machine vision applications. In a display application these bits are typically assigned as: Bit 26 –
DE, Bit 24 – HS, Bit 25 – VS. In the machine vision standard, Camera Link, these bits are typically assigned: Bit
26 – DVAL, Bit 24 – LVAL, Bit 25 – FVAL.
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following
restrictions:
• Normal Mode with Control Signal Filter Enabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3
PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
– DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition
pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal
can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency
noise on the control signals. See Figure 25.
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