DS92LV0421_15 Datasheet, PDF (24/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
www.ti.com
PCLK
IN
HS/VS/DE
IN
PCLK
OUT
Latency
HS/VS/DE
OUT
Pulses 1 or 2
PCLKs wide
Filetered OUT
Figure 25. Video Control Signal Filter Waveform
SERIALIZER Functional Description
The Ser converts a Channel Link LVDS clock and data bus to a single serial output data stream, and also acts
as a signal generator for the chipset Built In Self Test (BIST) mode. The device can be configured via external
pins or through the optional serial control bus. The Ser features enhanced signal quality on the link by
supporting: a selectable VOD level, a selectable de-emphasis signal conditioning and also the Channel Link II
data coding that provides randomization, scrambling, and DC Balancing of the data. The Ser includes multiple
features to reduce EMI associated with display data transmission. This includes the randomization and
scrambling of the serial data and also the system spread spectrum clock support. The Ser features power saving
features with a sleep mode, auto stop clock feature, and optional 1.8 V or 3.3V I/O compatibility.
See also Optional Serial Bus Control and Built In Self Test (BIST).
EMI Reduction Features
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process which enables the use of AC coupled interconnects
and also helps to manage EMI. The serializer first passes the parallel data through a scrambler which
randomizes the data. The randomized data is then DC balanced. The DC balanced and randomized data then
goes through a bit shuffling circuit and is transmitted out on the serial line. This encoding process helps to
prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges
from the parallel clock frequency to the nyquist rate. For example, if the Ser / Des chip set is operating at a
parallel clock frequency of 50 MHz, the resulting frequency content of serial stream ranges from 50 MHz to 700
MHz ( 50 MHz *28 bits = 1.4 Gbps / 2 = 700 MHz ).
Ser — Spread Spectrum Compatibility
The RxCLKIN of the Channel Link input is capable of tracking spread spectrum clocking (SSC) from a host
source. The RxCLKIN will accept spread spectrum tracking up to 35kHz modulation and ±0.5, ±1 or ±2%
deviations (center spread). The maximum conditions for the RxCLKIN input are: a modulation frequency of
35kHz and amplitude deviations of ±2% (4% total).
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