DS92LV0421_15 Datasheet, PDF (22/48 Pages) Texas Instruments – 10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

DS92LV0421, DS92LV0422
SNLS325C – MAY 2010 – REVISED APRIL 2013
www.ti.com
CON
FIG1
L
L
H
H
CON
FIG0
L
H
L
H
Table 1. DS92LV0421 Configuration Modes
Mode
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible
Backwards Compatible
Des Device
DS92LV0422,
DS92LV2422
DS92LV0422,
DS92LV2422
DS90UR124,
DS99R124
DS90C124
CON
FIG1
L
L
H
H
CON
FIG0
L
H
L
H
Table 2. DS92LV0422 Configuration Modes
Mode
Normal Mode, Control Signal Filter disabled
Normal Mode, Control Signal Filter enabled
Backwards Compatible
Backwards Compatible
Des Device
DS92LV0421,
DS92LV2421
DS92LV0421,
DS92LV2421
DS90UR241,
DS99R421
DS90C241
BIT MAPPING SELECT
The DS92LV0421 and DS92LV0422 can be configured to accept the LVDS parallel data with 2 different mapping
schemes: LSBs on RxIN[3] shown in Figure 23 or MSBs on RxIN[3] shown in Figure 24. The user selects which
mapping scheme is controlled by MAPSEL pin or by Register.
IMPORTANT NOTE — while the LVDS interface has 28 bits defined, only 27 bits are recovered by the SER and
sent to the DES. This supports 24 bit RGB plus the three video control signals. The 28th bit is not sampled, sent
or recovered.
RxCLKIN +/-
RxIN3 +/-
RxIN2 +/-
RxIN1 +/-
RxIN0 +/-
Previous cycle
DE
(bit 20)
B[1]
(bit 26)
VS
(bit 19)
Current cycle
B[0]
(bit 25)
HS
(bit 18)
G[1]
(bit 24)
G[0]
(bit 23)
B[7]
(bit 17)
B[6]
(bit 16)
R[1]
(bit 22)
B[5]
(bit 15)
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
Figure 23. 8–bit Channel Link Mapping: LSB's on RxIN3
R[3]
(bit 1)
R[0]
(bit 21)
B[4]
(bit 14)
G[3]
(bit 7)
R[2]
(bit 0)
22
Submit Documentation Feedback
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: DS92LV0421 DS92LV0422