DS125BR820 Datasheet, PDF (49/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

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DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
Typical Applications (continued)
8.2.3.2 Design Procedure
In PCIe Gen-3 applications, there is a large range of flexibility regarding the placement of the DS125BR820 in
the signal path due to the high linearity of the device. If the PCIe slot must also support lower speeds like PCIe
Gen-1 (2.5 Gbps) and Gen-2 (5.0 Gbps), it is recommended to place the DS125BR820 closer to the endpoint Rx.
Once the DS125BR820 is placed on the signal path, the repeater must be tuned. To tune the repeater, the
settings mentioned in Table 11 (for Pin Mode) and Table 12 (for SMBus Modes) are recommended as a default
starting point for most applications. Once these settings are configured, additional tuning of the EQ and, to a
lesser extent, VOD may be required to optimize the repeater performance to pass link training preset
requirements for PCIe Gen-3.
An example of a test configuration used to evaluate the DS125BR820 in this application can be seen in
Figure 40. For more information about DS125BR820 PCIe applications, please refer to application note
SNLA227:
PCIe Gen-3
Compliance
Base Board Riser
Lane Under
Test TX
Scope
Tektronix
DSA71604
PC Testing
Signal Test 3.2.0
Software
FR4 Trace
TL2
DS125BR820EVM
FR4 Trace
TL1
PCIe Gen 3.0 (x16 Lane)
^<v}Áv'}}_
Golden Graphics Card
TX: Front Side
RX: Back Side
Lane Under
Test RX
PCIe Connector
PCIe Gen-3
Compliance
Base Board
(CBB)
PCIe Gen-3 Preset
Configuration Control
Figure 40. Typical PCIe Gen-3 Add-In Card Test Diagram
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