DS125BR820 Datasheet, PDF (29/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

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DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
Address
Register
Name
0x11
CH0 - CHB_0
VOD_DB
0x12
CH0 - CHB_0
SD_TH
0x13-
0x14
Reserved
0x15
CH1 - CHB_1
RXDET
0x16
CH1 - CHB_1
EQ
Table 9. SMBus Slave Mode Register Map (continued)
Bit
Field
Type Default
EEPROM
Reg Bit
Description
7 RXDET Status
R
Observation bit for RXDET CH0 - CHB_0
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
6:5 Reserved
Set bits to 0
4:3 Reserved
Set bits to 0
0x02
2:0
VOD_DB ^R/W
Control
OUTB_0 VOD_DB Control
000'b = 0 dB (recommended)
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
Yes
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7
Reserved
Yes Set bit to 0
6:4 Reserved
Set bits to 0
Signal Detect
3:2 Status Assert
Threshold
R/W 0x00
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
01'b = 40 mVp-p
Yes 10'b = 75 mVp-p
11'b = 58 mVp-p
Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
Signal Detect
1:0
Status
De-assert
Threshold
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
01'b = 22 mVp-p
Yes 10'b = 55 mVp-p
11'b = 45 mVp-p
Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
7:0 Reserved R/W 0x00
Set bits to 0
7:6 Reserved
5:4 Reserved
R/W 0x00
3:2
RXDET
1:0 Reserved
7:0 EQ Control R/W 0x2F
Set bits to 0
Yes Set bits to 0
00'b = Input is Hi-Z impedance
01'b = Auto Rx-Detect,
outputs test every 12 ms for 600 ms (50 times) then
stops; termination is Hi-Z until detection; once detected
input termination is 50 Ω
Yes
10'b = Auto Rx-Detect,
outputs test every 12 ms until detection occurs;
termination is Hi-Z until detection; once detected input
termination is 50 Ω
11'b = Input is 50 Ω
Note: Override RXDET pin and enable register control
via Reg 0x08[3]
Set bits to 0
Yes
INB_1 EQ Control - total of four levels.
See Table 4.
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