DS125BR820 Datasheet, PDF (46/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
Typical Applications (continued)
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Time (20.83 ps/DIV)
No Repeater Used
TJ (1.0E-12) = Not Available Due to Closed Eye
Figure 31. TL1 = 15 Inch 5–Mil FR4 Trace,
TL2 = 10 Inch 5–Mil FR4 Trace,
No Repeater, 10.3125 Gbps
Time (16.16 ps/DIV)
DS125BR820 Settings: EQA = Level 4, VODA = Level 6
TJ (1.0E-12) = 47.9 ps
Figure 32. TL1 = 15 Inch 5–Mil FR4 Trace,
TL2 = 10 Inch 5–Mil FR4 Trace,
DS125BR820 CHA_0, 10.3125 Gbps
8.2.2 Front Port Applications (40G-CR4/SR4/LR4)
The DS125BR820 can be used in front port applications to extend the reach between the host ASIC and the
front-port cage. Front port applications typically include 40G-CR4/SR4/LR4. For 40GbE front port optical
protocols like 40G-SR4/LR4, the DS125BR820 is designed to support the front-port eye mask and jitter
requirements of applicable standards like nPPI. For 40GbE front port copper protocols like 40G-CR4, the
DS125BR820 is designed to provide channel equalization in a transparent fashion so as not to inhibit
IEEE802.3ba Clause 72 link training. In all of these front port cases, the DS125BR820 can also be used to
support eye mask and jitter requirements for SFF-8431 if the 40GbE QSFP+ port is intended to support 4x10G
SFP+ applications as well. Below is a typical example of the DS125BR820 used in a front port line-card
application.
Line Card
ASIC
FPGA
2x40G
DS125BR820
DS125BR820
2x40G
Stacked QSFP+
40GbE Copper CR4 or
40GbE SR4/LR4 Optical
8x10G
DS125BR820
DS125BR820
8x10G
Stacked QSFP+
1xQSFP+ to 4xSFP+
Breakout
Figure 33. Typical Front-Port System Configuration
8.2.2.1 Design Requirements
As with any high speed design, there are many factors that influence the overall performance. Please reference
Design Requirements in the Generic High Speed Repeater application section for a list of critical areas for
consideration and study during design.
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