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DS125BR820 Datasheet, PDF (25/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater
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DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
7.7 Register Maps
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. Tie ENSMB = 1
kΩ to VDD (2.5 V mode) or VIN (3.3 V mode) to enable SMBus Slave Mode and allow access to the
configuration registers.
The DS125BR820 uses AD[3:0] inputs in both SMBus Modes. These AD[3:0] pins are the user set SMBus slave
address inputs and have internal pull-downs. Based on the SMBus 2.0 specification, the DS125BR820 has a 7-
bit slave address. The LSB is set to 0'b (for a WRITE). When AD[3:0] pins are left floating or pulled low, AD[3:0]
= 0000'b, and the device default address byte is 0xB0. The device supports up to 16 address bytes, as shown in
Table 8:
AD[3:0] SETTINGS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 8. Device Slave Address Bytes
FULL SLAVE ADDRESS BYTE
(7-Bit ADDRESS + WRITE BIT)
B0
B2
B4
B6
B8
BA
BC
BE
C0
C2
C4
C6
C8
CA
CC
CE
7-Bit SLAVE
ADDRESS (HEX)
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
The SDA/SCL pins are 3.3 V tolerant, but are not 5V tolerant. An external pull-up resistor is required on the SDA
line. The resistor value can be from 2 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may
also require an external pull-up resistor and it depends on the Host that drives the bus.
7.7.1 Transfer Of Data Via The SMBus
During normal operation, the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH, then the bus transfers to the IDLE state.
7.7.2 SMBus Transactions
The device supports WRITE and READ transactions. See Table 9 for register address, type (Read/Write, Read
Only), default value, and function information.
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