DS125BR820 Datasheet, PDF (14/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
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Functional Block Diagram (continued)
7.2.1 Functional Datapath Blocks
In an increasing number of high speed applications, transparency between Tx and Rx endpoints is essential to
ensure high signal integrity. The DS125BR820 channel datapath uses one input gain stage equalization coupled
with a linear driver. This combination provides a high level of transparency, thereby achieving greater drive
distance in applications such as 40G-CR4, 40G-KR4, SAS, SATA, and PCIe that require Rx-Tx auto-negotiation
and link-training. Refer to the Typical Applications section for more application information regarding
recommended settings and placement.
7.3 Feature Description
The 4-level input pins use a resistor divider to help set the four valid control levels and provide a wider range of
control settings when ENSMB = 0. There is an internal 30 kΩ pull-up and a 60 kΩ pull-down connected to the
package pin. These resistors, together with the external resistor connection, combine to achieve the desired
voltage level. By using the 1 kΩ pull-down, 20 kΩ pull-down, no connect, and 1 kΩ pull-up, the optimal voltage
levels for each of the four input states are achieved as shown in Table 1.
Table 1. 4–Level Control Pin Settings
LEVEL
0
R
F
1
SETTING
Tie 1 kΩ to GND
Tie 20 kΩ to GND
Float (leave pin open)
Tie 1 kΩ to V_IN or V_DD
RESULTING PIN VOLTAGE
3.3 V MODE
2.5 V MODE
0.10 V
0.08 V
1/3 x V_IN
2/3 x V_IN
V_IN - 0.05 V
1/3 x V_DD
2/3 x V_DD
V_DD - 0.04 V
Typical 4-Level Input Thresholds
• Internal Threshold between 0 and R = 0.2 * V_IN or V_DD
• Internal Threshold between R and F = 0.5 * V_IN or V_DD
• Internal Threshold between F and 1 = 0.8 * V_IN or V_DD
In order to minimize the startup current associated with the integrated 2.5 V regulator, the 1 kΩ pull-up / pull-
down resistors are recommended. If several four level inputs require the same setting, it is possible to combine
two or more 1 kΩ resistors into a single lower value resistor. As an example, combining two inputs with a single
500 Ω resistor is a valid way to save board space.
7.4 Device Functional Modes
7.4.1 Pin Control Mode:
When in Pin Mode (ENSMB = 0), equalization and VOD (output amplitude) can be selected via pin control for
both the A-channels and B-channels per Table 4. The RXDET pin provides either automatic or manual control for
input termination (50 Ω or > 50 kΩ to VDD). The receiver electrical signal detect status threshold is adjustable via
the SD_TH pin. By setting signal-detect threshold level via the SD_TH pin, status information about a valid signal
detect assert/de-assert can be read back via SMBus registers. Pin control mode is ideal in situations where
neither MCU or EEPROM is available to access the device via SMBus SDA/SCL lines.
7.4.2 Slave SMBus Mode:
When in Slave SMBus Mode (ENSMB = 1), the VOD (output amplitude), equalization, and termination disable
features are all programmable on an individual channel basis, rather than in collective A-channel and B-channel
groups. Upon assertion of ENSMB, the EQx and VODx settings are controlled by SMBus immediately. It is
important to note that SMBus settings can only be changed from their defaults after asserting Register Enable by
setting Reg 0x06[3] = 1. The EQx and VODx pins are subsequently converted to AD0-AD3 SMBus address
inputs. The other external control pins (RXDET and SD_TH) remain active unless their respective registers are
written to and the appropriate override bit is set. If the user overrides a pin control, the input voltage level of that
control pin is ignored until ENSMB is driven low (Pin Mode). In the event that channels are powered down via the
PWDN pin, the state of all register settings are not affected.
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