DS125BR820 Datasheet, PDF (33/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

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DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
Address
Register
Name
0x26
CH3 - CHB_3
VOD_DB
0x27
CH3 - CHB_3
SD_TH
0x28
Signal Detect
Status Control
0x29-
0x2A
Reserved
Table 9. SMBus Slave Mode Register Map (continued)
Bit
Field
Type Default
EEPROM
Reg Bit
Description
7 RXDET Status
R
Observation bit for RXDET CH3 - CHB_3
1 = Input 50 Ω terminated to VDD
0 = Input is Hi-Z
6:5 Reserved
Set bits to 0
4:3 Reserved
Set bits to 0
0x02
2:0
VOD_DB ^R/W
Control
OUTB_3 VOD_DB Control
000'b = 0 dB (recommended)
001'b = –1.5 dB
010'b = –3.5 dB (default)
011'b = –5 dB
Yes
100'b = –6 dB
101'b = –8 dB
110'b = –9 dB
111'b = –12 dB
Note: Changing VOD_DB bits effectively lowers the
output VOD dynamic range by a factor of the
corresponding amount of dB reduction.
7
Reserved
Yes Set bit to 0
6:4 Reserved
Set bits to 0
Signal Detect
3:2 Status Assert
Threshold
R/W 0x00
Status Assert threshold (1010 pattern 12 Gbps)
00'b = 50 mVp-p (default)
01'b = 40 mVp-p
Yes 10'b = 75 mVp-p
11'b = 58 mVp-p
Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
Signal Detect
1:0
Status
De-assert
Threshold
Status De-assert threshold (1010 pattern 12 Gbps)
00'b = 37 mVp-p (default)
01'b = 22 mVp-p
Yes 10'b = 55 mVp-p
11'b = 45 mVp-p
Note: Override SD_TH pin and enable register control
via Reg 0x08[6]
7
Reserved
Set bit to 0
6
Reserved
Yes Set bit to 1
5:4
High SD_TH
Status
Enable Higher Range of Signal Detect Status
Yes
Thresholds
[5]: CH0 - CH3
[4]: CH4 - CH7
R/W 0x4C
3:2
Fast Signal
Detect Status
Enable Fast Signal Detect Status
[3]: CH0 - CH3
Yes [2]: CH4 - CH7
Note: In Fast Signal Detect, assert/de-assert response
occurs after approximately 3-4 ns
1:0
Reduced SD
Status Gain
Enable Reduced Signal Detect Status Gain
Yes [1]: CH0 - CH3
[0]: CH4 - CH7
7:0 Reserved R/W 0x00
Set bits to 0
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