DS125BR820 Datasheet, PDF (4/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
www.ti.com
PIN
NAME
NO.
DIFFERENTIAL HIGH SPEED I/O
INB_0+, INB_0- ,
1, 2
INB_1+, INB_1-,
3, 4
INB_2+, INB_2-,
5, 6
INB_3+, INB_3-
7, 8
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-
45, 44
43, 42
40. 39
38, 37
INA_0+, INA_0- ,
INA_1+, INA_1-,
INA_2+, INA_2-,
INA_3+, INA_3-
10, 11
12, 13
15, 16
17, 18
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34
33, 32
31, 30
29, 28
CONTROL PINS — SHARED (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBus SLAVE MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
RESERVED2
21
RESERVED3
19
Pin Functions⁽¹⁾
I/O, TYPE
PIN DESCRIPTION
I, CML
O, CML
I, CML
O, CML
Inverting and non-inverting CML differential inputs to the equalizer.
On-chip 50 Ω termination resistor connects INB_n+ to VDD and INB_n-
to VDD depending on the state of RXDET. See Table 2.
AC coupling required on high-speed I/O
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC
coupled CML inputs.
AC coupling required on high-speed I/O
Inverting and non-inverting CML differential inputs to the equalizer.
On-chip 50 Ω termination resistor connects INA_n+ to VDD and INA_n-
to VDD depending on the state of RXDET. See Table 2.
AC coupling required on high-speed I/O
Inverting and non-inverting 50 Ω driver outputs. Compatible with AC
coupled CML inputs.
AC coupling required on high-speed I/O
I, 4-LEVEL,
LVCMOS
System Management Bus (SMBus) Enable Pin
Tie 1 kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (SMBus Master Mode)
Tie 1 kΩ to GND = Pin Mode
I, LVCMOS,
O, OPEN Drain
I, LVCMOS,
O, OPEN Drain
I, LVCMOS
I, 4-LEVEL,
LVCMOS
I, 4-LEVEL,
LVCMOS
In SMBus Slave Mode, this pin is the SMBus clock I/O. Clock input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as
per SMBus interface standards⁽²⁾
In both SMBus Modes, this pin is the SMBus data I/O. Data input or
open drain output.
External 2 kΩ to 5 kΩ pull-up resistor to VDD or VIN recommended as
per SMBus interface standards⁽²⁾
SMBus Slave Address Inputs. In both SMBus Modes, these pins are the
user set SMBus slave address inputs.
External 1 kΩ pull-up or pull-down recommended.
Note: In Pin Mode, AD2 must be tied via external 1 kΩ to GND.
Reserved
For applications requiring Signal Detect status register read-back:
● Leave Pin 21 floating.
● Write Reg 0x08[2] = 1 if Pin 21 is floating.
Otherwise, tie Pin 21 via external 1 kΩ to GND (External 1 kΩ to VDD is
also acceptable).
Reserved
This input may be left floating, tied via 1 kΩ to VDD, or tied via 1 kΩ to
GND.
(1) LVCMOS inputs without the “Float” conditions must be driven to a logic low or high at all times or operation is not ensured.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
For 3.3 V mode operation, VIN pin input = 3.3 V and the logic "1" or "high" reference for the 4-level input is 3.3 V.
For 2.5 V mode operation, VDD pin output= 2.5 V and the logic "1" or "high" reference for the 4-level input is 2.5 V.
(2) SCL and SDA pins can be tied either to 3.3 V or 2.5 V, regardless of whether the device is operating in 2.5 V mode or 3.3 V mode.
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