DS125BR820 Datasheet, PDF (41/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

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REGISTER
0x18
0x1D
0x1E
0x1F
0x24
0x25
0x26
0x2C
0x2D
0x2E
0x33
0x34
0x35
0x3A
0x3B
0x3C
0x41
0x42
0x43
DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
Table 13. SMBus Example Sequence (continued)
WRITE VALUE
0x00
0x00
0xAE
0x00
0x00
0xAE
0x00
0x00
0xAE
0x00
0x00
0xAE
0x00
0x00
0xAE
0x00
0x00
0xAE
0x00
Set CHB_1 VOD_DB to 000'b.
Set CHB_2 EQ to 0x00.
Set CHB_2 VOD to 110'b.
Set CHB_2 VOD_DB to 000'b.
Set CHB_3 EQ to 0x00.
Set CHB_3 VOD to 110'b.
Set CHB_3 VOD_DB to 000'b.
Set CHA_0 EQ to 0x00.
Set CHA_0 VOD to 110'b.
Set CHA_0 VOD_DB to 000'b.
Set CHA_1 EQ to 0x00.
Set CHA_1 VOD to 110'b.
Set CHA_1 VOD_DB to 000'b.
Set CHA_2 EQ to 0x00.
Set CHA_2 VOD to 110'b.
Set CHA_2 VOD_DB to 000'b.
Set CHA_3 EQ to 0x00.
Set CHA_3 VOD to 110'b.
Set CHA_3 VOD_DB to 000'b.
COMMENTS
8.1.2 Signal Integrity in 40G-SR4/LR4 Applications
In 40G-SR4/LR4 applications, the ideal device settings must be tuned. In particular, EQ and VOD settings must
be optimized in order to aid the link partners in meeting the nPPI eye mask test. While tuning the DS125BR820
contributes to signal quality improvement, it is equally important to ensure that the link partner ASIC Tx FIR
signal characteristics are optimized as well to facilitate error-free data transmission. Suggested settings for the A-
channels and B-channels in a 40G-SR4/LR4 environment can be referenced in Table 11 and Table 12.
8.1.3 Rx Detect Functionality in 40G-CR4/KR4/SAS/SATA Applications
Unlike PCIe systems, 40G-CR4/KR4/SAS/SATA systems use a low speed communications sequence to detect
and communicate device capabilities between host ASIC and link partners. This communication eliminates the
need to detect for endpoints like in a PCIe application. For 40G-CR4/KR4/SAS/SATA systems, it is
recommended to tie the RXDET pin high. This ensures any link-training sequences sent by the host ASIC can
reach the link partner receiver without any additional latency due to termination detection sequences.
8.2 Typical Applications
8.2.1 Generic High Speed Repeater
The DS125BR820 extends PCB and cable reach in multiple applications by using active linear equalization. The
high linearity of this device aids specifically in protocols requiring link training and can be used in line cards,
backplanes, motherboards, and active cable assemblies, thereby improving margin and overall eye performance.
The capability of the repeater can be explored across a range of data rates and ASIC-to-link-partner signaling, as
shown in the following two test setup connections.
Pattern
Generator
V_OD = 1.0 Vp-p,
DE = 0 dB
PRBS15
TL
Lossy Channel
IN DS125BR820 OUT
Scope
BW = 60 GHz
Figure 9. Test Setup Connections Diagram
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