DS125BR820 Datasheet, PDF (1/62 Pages) Texas Instruments – Low-Power 12.5 Gbps 8-Channel Linear Repeater

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DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
DS125BR820 Low-Power 12.5 Gbps 8-Channel Linear Repeater
1 Features
•1 Low 70 mW/Channel (Typ) Power Consumption,
with Option to Power Down Unused Channels
• Seamless Link Training Support
• Enables Host ASIC to Meet Front-Port Eye Mask
Requirements over Longer Reach
• Advanced Configurable Signal Conditioning I/O
– Receive CTLE up to 10 dB at 6 GHz
– Linear Output Driver
– Variable Output Voltage Range up to 1200
mVp-p
• Programmable via Pin Selection, EEPROM, or
SMBus Interface
• Single Supply Voltage: 2.5 V or 3.3 V
• −40°C to 85°C Operating Temperature Range
• Flow-Thru Layout in 10 mm × 5.5 mm 54-Pin
Leadless WQFN Package
2 Applications
• Front-Port 40G-CR4/SR4/LR4 Link Extension
• Backplane 40G-KR4 Link Extension
• SAS/SATA/PCIe Link Extension
• Other Proprietary High Speed Interfaces up to
12.5 Gbps
Simplified Functional Block Diagram
INB_0+
.
INB_. _0-
.
.
.
.
INB_3+
INB_3-
OUTB_0+
.
OUTB__.0-
.
.
.
.
.
.
.
OUTB_3+
OUTB_3-
INA_0+
.
INA_. _0-
.
.
.
.
INA_3+
INA_3-
OUTA_0+
.
OUTA__.0-
.
.
.
.
.
.
.
OUTA_3+
OUTA_3-
Address
straps
(pull-up or
pull-down)
SMBus
Slave Mode⁽¹⁾
AD0
AD1
AD2
AD3
READ_EN
2.5V
2.5 V
Mode⁽³⁾
10F 1F
0.1F
(5x)
VIN
VDD_SEL
VDD
ENSMB
SDA⁽²⁾
SCL⁽²⁾
ALL_DONE
GND
VDD
SMBus
Slave Mode⁽¹⁾
To system
SMBus
3 Description
The DS125BR820 is an extremely low-power high-
performance repeater/redriver designed to support
eight channels carrying high speed interface up to
12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA,
and PCIe. The receiver's continuous time linear
equalizer (CTLE) provides high frequency boost that
is programmable from 3 to 10 dB at 6 GHz (12 Gbps)
followed by a linear output driver. The CTLE receiver
is capable of opening an input eye that is completely
closed due to inter symbol interference (ISI) induced
by interconnect medium such as board traces or twin
axial-copper cables. The programmable equalization
maximizes the flexibility of physical placement within
the interconnect channel and improves overall
channel performance.
When operating in 40G-CR4/KR4, SAS/SATA, and
PCIe applications, the DS125BR820 preserves
transmit signal characteristics, thereby allowing the
host controller and the end point to negotiate transmit
equalizer coefficients. This transparency in the link
training protocol facilitates system level
interoperability and minimizes latency.
The programmable settings can be applied easily via
pin control, software (SMBus or I2C), or direct loading
from an external EEPROM. In EEPROM mode, the
configuration information is automatically loaded on
power up, thereby eliminating the need for an
external microprocessor or software driver.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS125BR820
WQFN (54)
10 mm × 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram
Line Card
ASIC
FPGA
2x40G
DS125BR820
DS125BR820
2x40G
Stacked QSFP+
40GbE Copper CR4 or
40GbE SR4/LR4 Optical
8x10G
DS125BR820
DS125BR820
8x10G
Stacked QSFP+
1xQSFP+ to 4xSFP+
Breakout
(1) Schematic requires different connections for SMBus Master Mode and Pin Mode
(2) SMBus signals need to be pulled up elsewhere in the system.
(3) Schematic requires different connections for 3.3 V mode
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.