DS90UH925Q Datasheet, PDF (42/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
Applications Information
DISPLAY APPLICATION
The DS90UH925Q, in conjunction with the DS90UH926Q, is intended for interface between a HDCP compliant host (graphics
processor) and a Display. It supports a 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive
a three 8-bit RGB stream with a pixel rate up to 85 MHz together with three control bits (VS, HS and DE) and three I2S-bus audio
stream with an audio sampling rate up to 192 kHz. The included HDCP 1.3 compliant cipher block allows the authentication of the
DS90UH926Q, which decrypts both video and audio contents. The keys are pre-loaded by TI into Non-Volatile Memory (NVM) for
maximum security.
TYPICAL APPLICATION CONNECTION
Figure 21 shows a typical application of the DS90UH925Q serializer for an 85 MHz 24-bit Color Display Application. The CML
outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines. The serializer has an internal termination.
Bypass capacitors are placed near the power supply pins. At a minimum, six (6) 4.7μF capacitors (and two (2) additional 1μF
capacitors should be used for local device bypassing. Ferrite beads are placed on the two (2) VDDs (V_DD33 and V_DDIO) for effective
noise suppression. The interface to the graphics source is with 3.3V LVCMOS levels, thus the V_DDIO pin is connected to the 3.3 V
rail. A RC delay is placed on the PDB signal to delay the enabling of the device until power is stable.
FIGURE 21. Typical Connection Diagram
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