DS90UH925Q Datasheet, PDF (19/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
I2S TRANSMITTING
In normal 24-bit RGB operation mode, the DS90UH925Q supports 3 bits of I2S. They are I2S_CLK, I2S_WC and I2S_DA. The
optionally encrypted and packetized audio information can be transmitted during the video blanking (data island transport) or during
active video (forward channel frame transport). Note: The bit rates of any I2S bits must maintain one fourth of the PCLK rate. The
audio encryption capability is supported per HDCP v1.3.
Secondary I2S Channel
In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio in addition to the 3–
bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA and I2S_WC at the input to the serializer.
This operation mode is enabled through either the MODE_SEL pin (Table 1) or through the register bit 0x12[0] (Table 6).
Table 4 below covers the range of I2S sample rates.
Sample Rate (kHz)
32
44.1
48
96
192
32
44.1
48
96
192
32
44.1
48
96
192
TABLE 4. Audio Interface Frequencies
I2S Data Word Size (bits)
16
16
16
16
16
24
24
24
24
24
32
32
32
32
32
I2S CLK (MHz)
1.024
1.411
1.536
3.072
6.144
1.536
2.117
2.304
4.608
9.216
2.048
2.822
3.072
6.144
12.288
Copyright © 1999-2012, Texas Instruments Incorporated
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