DS90UH925Q Datasheet, PDF (15/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
VIDEO CONTROL SIGNAL FILTER
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:
• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the
transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no
restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual
display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See
Figure 10.
30136302
FIGURE 10. Video Control Signal Filter Waveform
EMI REDUCTION FEATURES
Input SSC Tolerance (SSCT)
The DS90UH925Q serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profile up to +/-2.5% amplitude
deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.
LVCMOS V_DDIO OPTION
1.8V or 3.3V Inputs and Outputs are powered from a separate V_DDIO supply to offer compatibility with external system interface
signals. Note: When configuring theV_DDIO power supplies, all the single-ended data and control input pins for device need to scale
together with the same operating V_DDIO levels.
POWER DOWN (PDB)
The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by the host or through
the V_DDIO, where V_DDIO = 3.0V to 3.6V or V_DD33. To save power disable the link when the display is not needed (PDB = LOW).
When the pin is driven by the host, make sure to release it after V_DD33 and V_DDIO have reached final levels; no external components
are required. In the case of driven by the V_DDIO = 3.0V to 3.6V or V_DD33 directly, a 10 kohm resistor to the V_DDIO = 3.0V to 3.6V or
V_DD33 , and a >10uF capacitor to the ground are required (See Figure 21 Typical Connection Diagram).
REMOTE AUTO POWER DOWN MODE
The Serializer features a remote auto power down mode. During the power down mode of the pairing deserializer, the Serializer
enters the remote auto power down mode. In this mode, the power dissipation of the Serializer is reduced significantly. When the
Deserializer is powered up, the Serializer enters the normal power on mode automatically. This feature is enabled through the
register bit 0x01[7] Table 6.
INPUT PCLK LOSS DETECT
The serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. A clock loss condition is
detected when PCLK drops below approximately 1MHz. When a PCLK is detected again, the serializer will then lock to the incoming
PCLK. Note – when PCLK is lost, the Serial Control Bus Registers values are still RETAINED.
Copyright © 1999-2012, Texas Instruments Incorporated
15