DS90UH925Q Datasheet, PDF (16/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
SERIAL LINK FAULT DETECT
The serial link fault detection is able to detect any of following seven (7) conditions
1) cable open
2) “+” to “-“ short
3) “+” short to GND
4) “-“ short to GND
5) “+” short to battery
6) “-“ short to battery
7) Cable is linked correctly
If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C Table 6.
PIXEL CLOCK EDGE SELECT (RFB)
The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determines the edge that the
data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFB is LOW (‘0’), data is latched on the
Falling edge of the PCLK.
LOW FREQUENCY OPTIMIZATION (LFMODE)
The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 1). It controls the operating frequency of the serializer. If
LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE is High, the PCLK frequency is between
5 MHz and <15 MHz. Please note when the device LFMODE is changed, a PDB reset is required.
INTERRUPT PIN — FUNCTIONAL DESCRIPTION AND USAGE (INTB)
1. On DS90UH925, set register 0xC6[5] = 1 and 0xC6[0] = 1
2. DS90UH926Q deserializer INTB_IN (pin 16) is set LOW by some downstream device.
3. DS90UH925Q serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an interrupt condition.
4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .
5. A read to HDCP_ISR will clear the interrupt at the DS90UH925, releasing INTB.
6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the
interrupt driving INTB_IN. This would be when the downstream device releases the INTB_IN (pin 16) on the DS90UH926Q.
The system is now ready to return to step (1) at next falling edge of INTB_IN.
CONFIGURATION SELECT (MODE_SEL)
Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and
a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL input (V_R4) and V_DD33 to select
one of the other 10 possible selected modes. See Figure 11 and Table 1.
30136341
FIGURE 11. MODE_SEL Connection Diagram
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