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DS90UH925Q Datasheet, PDF (38/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP
DS90UH925Q
ADD
(dec)
194
ADD Register
(hex) Name
0xC2 HDCP CFG
Bit(s)
7
6
5
4:3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x80
Function Description
ENH LV
Enable Enhanced Link Verification
Allows checking of the encryption Pj value on
every 16th frame
1: Enhanced Link Verification enabled
0: Enhanced Link Verification disabled
HDCP
EESS
Enables Enhanced Encryption Status Signaling
(EESS) instead of the Original Encryption Status
Signaling (OESS)
1: EESS mode enabled
0: OESS mode enabled
TX RPTR
Transmit Repeater Enable
Enables the transmitter to act as a repeater. In this
mode, the HDCP Transmitter incorporates the
additional authentication steps required of an
HDCP Repeater.
1: Transmit Repeater mode enabled
0: Transmit Repeater mode disabled
ENC Mode Encryption Control Mode
Determines mode for controlling whether
encryption is required for video frames
00: Enc_Authenticated
01: Enc_Reg_Control
10: Enc_Always
11: Enc_InBand_Control (per frame)
If the Repeater strap option is set at power-up,
Enc_InBand_Control (ENC_MODE == 11) will be
se-lected. Otherwise, the default will be
Enc_Authenticated mode (ENC_MODE == 00).
Wait
Enable 100ms Wait
The HDCP 1.3 specification allows for a 100ms
wait to allow the HDCP Receiver to compute the
initial encryption values. The FPD-Link III
implementation guarantees that the Receiver will
complete the computations before the HDCP
Transmitter. Thus the timer is unnecessary. To
enable the 100ms timer, set this bit to a 1.
RX DET
SEL
RX Detect Select
Controls assertion of the Receiver Detect
Interrupt. If set to 0, the Receiver Detect Interrupt
will be asserted on detection of an FPD-Link III
Receiver. If set to 1, the Receiver Detect Interrupt
will also require a receive lock indication from the
receiver.
HDCP AV
MUTE
Enable AVMUTE
Setting this bit to a 1 will initiate AVMUTE
operation. The transmitter will ignore encryption
status controls while in this state. If this bit is set to
a 0, normal operation resumes. This bit may only
be set if the HDCP_EESS bit is also set.
38
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