DS90UH925Q Datasheet, PDF (14/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
Functional Description
The DS90UH925Q serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to 2.975 Gbps line rate.
The serial stream contains an embedded clock, video control signals and DC-balanced video data and audio data which enhance
signal quality to support AC coupling. The DS90UH925Q serializes video and audio data then applies encryption through a High-
Bandwidth Digital Content Protection (HDCP) Cipher and transmits out through the FPD-Link III interface. Audio encryption is
supported. The serializer also includes the HDCP cipher. On board non-volatile memory stores the HDCP keys. All key exchange
is conducted over the FPD-Link III bidirectional control interface. The serializer is intended for use with the DS90UH926Q deseri-
alizer, but is also backward compatible with DS90UR906Q or DS90UR908Q FPD-Link II deserializer.
HIGH SPEED FORWARD CHANNEL DATA TRANSFER
The High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals, HDCP, I2C, and
I2S audio transmitted from Serializer to Deserializer. Figure 9 illustrates the serial stream per PCLK cycle. This data payload is
optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled.
FIGURE 9. FPD-Link III Serial Stream
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The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbps maximum (175 Mbps
minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.
LOW SPEED BACK CHANNEL DATA TRANSFER
The Low-Speed Backward Channel (LS_BC) of the DS90UH925Q provides bidirectional communication between the display and
host processor. The information is carried back from the Deserializer to the Serializer per serial symbol. The back channel control
data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock
information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back
channel contains the I2C, HDCP, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.
BACKWARD COMPATIBLE MODE
The DS90UH925Q is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link II deserializers at 5-65 MHz of
PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating at the line rate of 140 Mbps to 1.82 Gbps. The
backward configuration mode can be set via MODE_SEL pin (Table 1) or the configuration register (Table 6). Note: frequency
range = 15 - 65MHz when LFMODE = 0 and frequency range = 5 - <15MHz when LFMODE = 1.
COMMON MODE FILTER PIN (CMF)
The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pin for additional
common-mode filtering of the differential pair. This can be useful in high noise environments for additional noise rejection capability.
A 0.1 μF capacitor must be connected to this pin to Ground.
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