DS90UH925Q Datasheet, PDF (39/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
ADD
(dec)
195
ADD Register
(hex) Name
0xC3 HDCP CTL
Bit(s)
7
6
5
4
3
2
1
0
Register
Type
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
Function Description
HDCP
RST
HDCP Reset
Setting this bit will reset the HDCP transmitter and
disable HDCP authentication. This bit is self-
clearing.
Reserved
KSV List
Valid
The controller sets this bit after validating the
Repeater’s KSV List against the Key revocation
list. This allows completion of the Authentication
process. This bit is self-clearing
KSV Valid
The controller sets this bit after validating the
Receiver’s KSV against the Key revocation list.
This allows continuation of the Authentication
process. This bit will be cleared upon assertion of
the KSV_RDY flag in the HDCP_STS register.
Setting this bit to a 0 will have no effect
HDCP
ENC DIS
HDCP Encrypt Disable
Disables HDCP encryption. Setting this bit to a 1
will cause video data to be sent without encryption.
Authentication status will be maintained. This bit
is self-clearing
HDCP
ENC EN
HDCP Encrypt Enable
Enables HDCP encryption. When set, if the device
is authenticated, encrypted data will be sent. If
device is not authenticated, a blue screen will be
sent. Encryption should always be enabled when
video data requiring content protection is being
supplied to the transmitter. When this bit is not set,
video data will be sent without encryption. Note
that when CFG_ENC_MODE is set to
Enc_Always, this bit will be read only with a value
of 1
HDCP DIS HDCP Disable
Disables HDCP authentication. Setting this bit to
a 1 will disable the HDCP authentication.
This bit is self-clearing
HDCP EN
HDCP Enable/Restart
Enables HDCP authentication. If HDCP is already
enabled, setting this bit to a 1 will restart
authentication. Setting this bit to a 0 will have no
effect. A register read will return the current HDCP
enabled status
Copyright © 1999-2012, Texas Instruments Incorporated
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