DS90UH925Q Datasheet, PDF (3/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
Pin Descriptions
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
R[7:0]
34, 33, 32, 29, I, LVCMOS RED Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull down Leave open if unused
R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.
G[7:0]
42, 41, 40, 39, I, LVCMOS GREEN Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull down Leave open if unused
G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.
B[7:0]
2, 1, 48, 47, I, LVCOS BLUE Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull down Leave open if unused
B0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.
HS
3
I, LVCMOS Horizontal Sync Input Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 6
VS
4
I, LVCMOS Vertical Sync Input Pin
w/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width
is 130 PCLKs.
DE
5
I, LVCMOS Data Enable Input Pin
w/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the
Control Signal Filter is enabled. There is no restriction on the minimum transition pulse
when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130
PCLKs.
See Table 6
PCLK
10
I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. SeeTable 6
w/ pull down
I2S_CLK,
I2S_WC,
I2S_DA
13, 12, 11
I, LVCMOS Digital Audio Interface Data Input Pins
w/ pull down Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as
GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
Optional Parallel Interface
I2S_DB
44
I, LVCMOS Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by
w/ pull down MODE_SEL pin or configuration register
Leave open if unused
I2S_DB can optionally be used as B1 or GPO_REG5.
GPIO[3:0]
36, 35, 26, 25 I/O,
LVCMOS
w/ pull down
General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or
configuration register. SeeTable 6
Leave open if unused
Shared with G1, G0, R1 and R0.
GPO_REG 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6
[8:4]
43
w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.
Control
PDB
21
I, LVCMOS Power-down Mode Input Pin
w/ pull-down PDB = H, device is enabled (normal operation)
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL
is shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL
24
I, Analog Device Configuration Select. See Table 1
Copyright © 1999-2012, Texas Instruments Incorporated
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