DS90UH925Q Datasheet, PDF (33/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
ADD
(dec)
20
22
23
24
25
ADD
(hex)
0x14
Register
Name
Oscillator
Clock Source
and BIST
Status
Bit(s)
7:3
2:1
0
0x16 BCC
7:1
Watchdog
Control
0
0x17 I2C Control
7
6
5:4
3:0
0x18 SCL High Time 7:0
0x19 SCL Low Time 7:0
Register
Type
RW
R
RW
RW
RW
RW
RW
RW
RW
Default
(hex)
0x00
0xFE
0x5E
0xA1
0xA5
Function Description
Reserved
OSC Clock OSC Clock Source
Source (When LFMODE = 1, Oscillator = 12.5MHz ONLY)
00: External Pixel Clock
01: 33 MHz Oscillator
10: Reserved
11: 25 MHz Oscillator
BIST
Enable
Status
BIST status
1: Enabled
0: Disabled
Timer
Value
The watchdog timer allows termination of a control
channel transaction if it fails to complete within a
programmed amount of time.
This field sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2 ms.
This field should not be set to 0
Timer
Control
Disable Bidirectional Control Channel Watchdog
Timer
1: Disables BCC Watchdog Timer operation
0: Enables BCC Watchdog Timer operation
I2C Pass
All
I2C Control
1: Enable Forward Control Channel pass-through
of all I2C accesses to I2C Slave IDs that do not
match the Serializer I2C Slave ID.
0: Enable Forward Control Channel pass-through
only of I2C accesses to I2C Slave IDs matching
either the remote Deserializer Slave ID or the
remote Slave ID.
Reserved
SDA Hold
Time
Internal SDA Hold Time
Configures the amount of internal hold time
provided for the SDA input relative to the SCL
input. Units are 40 ns
I2C Filter
Depth
Configures the maximum width of glitch pulses on
the SCL and SDA inputs that will be rejected. Units
are 5 ns
SCL HIGH I2C Master SCL High Time
Time
This field configures the high pulse width of the
SCL output when the Serializer is the Master on
the local I2C bus. Units are 40 ns for the nominal
oscillator clock frequency. The default value is set
to provide a minimum 5us SCL high time with the
internal oscillator clock running at 32.5MHz rather
than the nominal 25MHz.
SCL LOW
Time
I2C SCL Low Time
This field configures the low pulse width of the SCL
output when the Serializer is the Master on the
local I2C bus. This value is also used as the SDA
setup time by the I2C Slave for providing data prior
to releasing SCL during accesses over the
Bidirectional Control Channel. Units are 40 ns for
the nominal oscillator clock frequency. The default
value is set to provide a minimum 5us SCL low
time with the internal oscillator clock running at
32.5MHz rather than the nominal 25MHz.
Copyright © 1999-2012, Texas Instruments Incorporated
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