DS90UH925Q Datasheet, PDF (4/47 Pages) Texas Instruments – 720p 24-bit Color FPD-Link III Serializer with HDCP

DS90UH925Q
Pin Name
Pin #
I/O, Type Description
I2C
IDx
6
I, Analog I2C Serial Control Bus Device ID Address Select
External pull-up to V_DD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure
17
SCL
8
I/O,
I2C Clock Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
SDA
9
I/O,
I2C Data Input / Output Interface
LVCMOS Must have an external pull-up to V_DD33, DO NOT FLOAT.
Open Drain _{Recommended pull-up: 4.7kΩ.}
Status
INTB
31
O, LVCMOS HDCP Interrupt
Open Drain INTB = H, normal
INTB = L, Interrupt request
FPD-Link III Serial Interface
Recommended pull-up: 4.7kΩ to V_DDIO
DOUT+
20
O, LVDS True Output
The output must be AC-coupled with a 0.1µF capacitor.
DOUT-
19
O, LVDS Inverting Output
The output must be AC-coupled with a 0.1µF capacitor.
CMF
23
Analog Common Mode Filter.
Connect 0.1µF to GND
Power^* and Ground
V_DD33
V_DDIO
GND
22
30
DAP
Power
Power
Ground
Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GND
LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GND
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
Regulator Capacitor
CAPHS12,
CAPP12
17, 14
CAP
Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at each
CAP pin.
CAPL12
7
CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this
CAP pin.
Others
NC
16
NC
Do not connect.
RES[1:0]
18, 15
GND Reserved. Tie to Ground.
*_{The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.}
4
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