LM3S1968 Datasheet, PDF (11/709 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S1968 Microcontroller
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 482
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 483
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 484
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 485
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 485
Figure 14-1. I²C Block Diagram ............................................................................................. 514
Figure 14-2. I²C Bus Configuration ........................................................................................ 515
Figure 14-3. START and STOP Conditions ............................................................................. 515
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 516
Figure 14-5. R/S Bit in First Byte ............................................................................................ 516
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 516
Figure 14-7. Master Single SEND .......................................................................................... 520
Figure 14-8. Master Single RECEIVE ..................................................................................... 521
Figure 14-9. Master Burst SEND ........................................................................................... 522
Figure 14-10. Master Burst RECEIVE ...................................................................................... 523
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 524
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 525
Figure 14-13. Slave Command Sequence ................................................................................ 526
Figure 15-1. Analog Comparator Module Block Diagram ......................................................... 551
Figure 15-2. Structure of Comparator Unit .............................................................................. 552
Figure 15-3. Comparator Internal Reference Structure ............................................................ 553
Figure 16-1. PWM Unit Diagram ............................................................................................ 564
Figure 16-2. PWM Module Block Diagram .............................................................................. 565
Figure 16-3. PWM Count-Down Mode .................................................................................... 567
Figure 16-4. PWM Count-Up/Down Mode .............................................................................. 567
Figure 16-5. PWM Generation Example In Count-Up/Down Mode ........................................... 568
Figure 16-6. PWM Dead-Band Generator ............................................................................... 568
Figure 17-1. QEI Block Diagram ............................................................................................ 603
Figure 17-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 605
Figure 18-1. 100-Pin LQFP Package Pin Diagram .................................................................. 620
Figure 18-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 621
Figure 21-1. Load Conditions ................................................................................................ 656
Figure 21-2. JTAG Test Clock Input Timing ............................................................................. 659
Figure 21-3. JTAG Test Access Port (TAP) Timing .................................................................. 659
Figure 21-4. JTAG TRST Timing ............................................................................................ 659
Figure 21-5. External Reset Timing (RST) .............................................................................. 660
Figure 21-6. Power-On Reset Timing ..................................................................................... 660
Figure 21-7. Brown-Out Reset Timing .................................................................................... 661
Figure 21-8. Software Reset Timing ....................................................................................... 661
Figure 21-9. Watchdog Reset Timing ..................................................................................... 661
Figure 21-10. Hibernation Module Timing ................................................................................. 662
Figure 21-11. ADC Input Equivalency Diagram ......................................................................... 663
Figure 21-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 664
Figure 21-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 665
Figure 21-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 665
Figure 21-15. I²C Timing ......................................................................................................... 666
Figure D-1. Stellaris LM3S1968 100-Pin LQFP Package Dimensions ..................................... 697
July 15, 2014
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