TL16C554 Datasheet, PDF (8/33 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT

TL16C554, TL16C554I
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165D – JANUARY 1994 – REVISED JULY 1998
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
td5 Delay time, INTx↓ to TXx↓ at start
TEST CONDITIONS
MIN MAX
8
24
td6 Delay time, TXx↓ at start to INTx↑
See Note 5
8
8
td7 Delay time, IOW high or low (WR THR) to INTx↑
See Note 5
16
32
td8 Delay time, TXx↓ at start to TXRDY↓
CL = 100 pF
8
tpd1 Propagation delay time, IOW (WR THR)↓ to INTx↓
CL = 100 pF
35
tpd2 Propagation delay time, IOR (RD IIR)↑ to INTx↓
CL = 100 pF
30
tpd3 Propagation delay time, IOW (WR THR)↑ to TXRDY↑
CL = 100 pF
50
NOTE 5: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.
UNIT
RCLK
cycles
RCLK
cycles
RCLK
cycles
RCLK
cycles
ns
ns
ns
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER
TEST CONDITIONS MIN MAX UNIT
td9 Delay time, stop bit to INTx↑ or stop bit to RXRDY↓ or read RBR to set interrupt
See Note 6
1
RCLK
cycle
tpd4 Propagation delay time, Read RBR/LSR to INTx↓/LSR interrupt↓
CL = 100 pF,
See Note 7
40 ns
tpd5 Propagation delay time, IOR RCLK↓ to RXRDY↑
See Note 7
30 ns
NOTES: 6. The receiver data available indicator, the overrun error indicator, the trigger level interrupts, and the active RXRDY indicator are
delayed three RCLK (internal receiver timing clock) cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
IOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, C_L = 100 pF (see Figure 14)
PARAMETER
MIN MAX UNIT
tpd6 Propagation delay time, IOW (WR MCR)↑ to RTSx, DTRx↑
tpd7 Propagation delay time, modem input CTSx, DSRx, and DCDx ↓↑ to INTx↑
tpd8 Propagation delay time, IOR (RD MSR)↑ to interrupt↓
tpd9 Propagation delay time, RIx↑ to INTx↑
50 ns
30 ns
35 ns
30 ns
8
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